50.4 Peripheral Dependencies

Peripheral

Name

Base AddressNVIC IRQ

Index: Source

MCLK AHBx/APBx

Clock Enable Mask Bit

GCLK Peripheral Channel

Clock Name:Register

PAC Peripheral Identifier

(PAC.WRCTRL.PERIDx)

EVSYS Generator

(EVSYS.CHANNELn.EVGENx)

DMA Trigger Index:Source

(DMAC.CHCTRLBk.TRIGx)

Power

Domain

I2S0x4501_6000140 : SPI_IXSMCLK.CLKMSK3[11]GCLK_SPI_IXS : PCHCTRL[36]47113 : GEN65 : RX

66 : TX

VDDREG

Power Management

The peripheral will continue to operate in any sleep mode where the selected source clocks are running.

Clocks

One clock, the GCLK_I2Sx is a required peripheral, GCLK_I2Sx can be set to a wide range of frequencies and clock sources. The GCLK_I2Sx must be enabled and configured before use. Refer to the clock peripheral configuration section for details on the GCLK_I2Sx configuration. The clock is only used in Host mode.

DMA

The IxS peripheral is connected to the DMA Controller (DMAC). Using the IxS DMA requests requires the DMA Controller to be configured first (Refer to DMAC section in this document).

Interrupts

The interrupt request line is connected to the interrupt controller (NVIC). Using the peripheral interrupt(s) requires the NVIC interrupt controller to be configured first.