50.5 Functional Description
SPI Overview
The Serial Peripheral Interface (SPI) is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. SPI communication is full-duplex, which means that transmission and reception proceed simultaneously. It is an example of synchronous communication, as both communicating entities use the same clock signal, and is compatible with Motorola's SPI and SIOP interfaces.
Legacy compatibility is kept for the 8-bit and 16-bit modes with the addition of 32-bit operation.
Audio Protocol Overview
This IxS peripheral adds support for Audio CODEC serial protocols such as I2S, Left Justified, Right Justified and PCM/DSP modes for 16, 24, and 32-bit audio data. The macro supports only half-duplex for audio communication. Also, the audio CODEC protocols differ from SPI as they require a free running clocks.
SPI Operation
When MODE_EN = 00 (AUDEN = 0 or TDM_EN =0 or TPD_EN = 0) the macro operates like a normal SPI protocol.
The serial port consists of a 32-bit register (SPIxSR) used for sending data in and out. A receive buffer (SPIxRXB) and a transmit buffer (SPIxTXB) share one SFR address, SPIxBUF. The control registers (SPIxCTRL_*) configures the peripheral, and the status register (SPIxSTAT) indicates various status conditions.
Four pins make up the serial interface:
- SDI: Serial Data Input
- SDO: Serial Data Output
- SCK: Shift Clock input or output
- SS/FSYNC: Active low Client Select, or Frame Synchronization pulse
For a SPI data transfer to take place between two devices, one device must be configured as a host and the other as a client. Host mode is enabled by setting the SPIxCTRL_*.MSTEN bit. The host generates the serial clock pulses and does so only when there is data to be transmitted. In other words, the host controls the rate at which the data bits get transmitted. So, SCK is clock output in Host mode while in Client mode, it is clock input.
The SS/FSYNC can be driven by the peripheral in host mode. FRMEN (FRMEN = TDM_EN || AUDEN ||TPD_EN) and SPIxCTRL_*.MSSEN register bits control this feature.