41.5 Clocks
The TRNG bus clock (CLK_TRNG_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_TRNG_APB can be found in Peripheral Clock Masking.
References:
The TRNG bus clock (CLK_TRNG_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_TRNG_APB can be found in Peripheral Clock Masking.
References:
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.