56 Revision History

Revision E - October 2024

SectionDescription
Configuration Summary
  • Added new tables to reflect new package offerings
Package and Pinout
Signal Descriptions
  • Updated all tables to display new pin counts for the 48-pin TQFP and 144-pin TFBGA
Power Supplies and Startup Considerations
Memories
SUPC
RSTC
  • Updated the BORVDDA bitfield of the RCAUSE Register with a new note
PORT
  • Added a new table to the PMUXm Register
TCC
CCL
ADC
  • Updated the input Signal names from AIN to VINP throughout the chapter
Electrical Characteristics
Packaging

Revision D - July 2024

SectionDescription
Package and Pinout
Signal Description
  • Updated Table 6-13 PORTA through PORTD Signals with a new pin number for PB00
Clock Distribution System
TrustRAM (TRAM)
Electrical Characteristics

Revision C - April 2024

SectionDescription
GeneralMinor changes of format.
  • VREFP0 changed by VREFH
  • SPIxC- TRL changed by SPIxCTRL
  • VDDF changed by VDDFLASH
  • ADC0 changed by ADC
  • ADCn changed by ADC
  • INSELx changed by INSELy
  • Remove VBAT references
Features
  • Updated info of USB2.0 and Advanced Analog Features and Touch. Removed NIST compliant information.
Configuration Summary
Guidelines for Getting Started
  • Replaced Pie-Filters by Pi-Filters in the EMI/EMC/EFT (IEC61000-4-4 and IEC 61000-4-2) Suppression Considerations section
Package and Pinout
Signal Description
  • Added info of 64-Pin and 100-Pin in all the tables
Power Supplies and Startup Considerations
Product Mapping
Peripherals
Processor and Architecture
Memories
Cortex-M Cache Controller (CMCC)
Peripheral Access Controller (PAC)
Device Service Unit (DSU)
Clock Distribution System
Oscillator Controller (OSCCTRL)
Generic Clock Controller (GCLK)
Main Clock (MCLK)
32 KHz Oscillators Controller (OSC32KCTRL)
Frequency Meter (FREQM)
  • Minor changes of format in Overview and Measurement sections
  • Added notes in SWRST bitfield in the CTRLA Register
  • Added note in REFNUM bitfield in the CFGA Register
Real-Time Counter (RTC)
Direct Memory Access Controller (DMAC)
  • Updated channels of DMA Controller modules 0 and 1
  • Updated DMA Event/Trigger Mapping
Supply Controller (SUPC)
Power Manager (PM)
Reset Controller (RSTC)
  • Removed VBAT reference in Features and the Reset Causes and Effects sections
External Interrupt Controller (EIC)
Event System (EVSYS)
Serial Communication Interface (SERCOM)
Serial Quad Interface (SQI)
  • Updated Chip Selects to 4
  • Updated Figure 35-1
  • Updated CSEN bitfield in CFG Register
Universal Serial Bus Hi-Speed (USBHS)
Controller Area Network (CAN)
True Random Number Generator (TRNG)
  • Updated second paragraph in Overview section
  • Removed one bullet in Features section
Configurable Custom Logic (CCL)
Analog-to-Digital Converter (ADC)
Analog Comparators (AC)
  • Updated MUXPOS bitfield in COMPCTRL0 Register
Position Decoder (PDEC)
Timer/Counter for Control Applications (TCC)
TrustRAM (TRAM)
  • Added note 4 in CTRLA Register
  • Added note 2 in CTRLA Register
Peripheral Touch Controller (PTC)
  • Minor changes in Clocks section
Electrical Characteristics
  • Updated Note 4

Revision B - May 2023

SectionDescription
General
  • Updated DPLL to read PLL throughout the document
Features
  • Updated Advanced Analog Features and Touch instances with new data for channel numbers
  • Reformatted the Communication Interfaces/Digital Peripherals section
  • Updated the DMA instances
Configuration Summary
  • Replaced the existing tables with all new content
Signal Description
  • Replaced the existing tables with all new content
Block Diagram
  • Updated the Diagram with a new image
Pinout
Power Supplies and Startup Considerations
Processor and Architecture
Memories
CMCC
  • Updated the WAYNUM bitfield in the TYPE Register with a new table
IDAU
  • This chapter was completely rewritten in this revision
DSU
  • Corrected erroneous bitfield output for the CPUx bitfield in the DAL Register
  • Removed an obsolete DATA Register Summary and associated Register
Clock Distribution System
OSCCTRL
GCLK
MCLK
OSC32KCTRL
  • Updated the CGM and STARTUP bitfields to properly display content in the XOSC32K Register
WDT
  • Updated the following registers to properly display bitfield information:
RTC
  • Updated the TAMPCTRL Register to properly display the INnACT bitfield output
SUPC
  • Removed erroneous LDO information from the Block Diagram
  • Removed erroneous bitfields for ULDOOVHEAT, and ULDORDY from the following registers:
  • Removed erroneous bitfields for BKUP_VLD, SRAM_VLD, ULDOLEVEL, ULDSTDBY, ULDOEN, and OFFSTDBY from the VREGCTRL Register
  • Added new information for the LVSTDBY and VREGOUT bitfields in the VREGCTRL Register
RSTC
NVMCTRL
ADC
Electrical Specifications 85°C
Extended Temperature Electrical Characterstics (125°C)
  • All new section
Schematic Checklist
  • Updated the voltage specifications in the Diagram in Introduction
Packaging

Revision A - November 2022

Terminology used in this document may not match with the contents of other Microchip documentation and collateral. For any questions or concerns regarding terminology, contact a Microchip support or sales representative.

This is the initial released version of this document.