25.5 Indexing
There are 8 DMA channels on module 0 and 4 DMA channels on module 1, indexed by k, k = 0,1,…,n. Each channel has 19 dedicated channel-specific registers, which are identified by the channel index as a suffix:
CHCTRLAk - Channel Control Register A
CHCTRLBk - Channel Control Register B
CHEVCTRLk - Channel Event Control Register
CHINTENCLRk - Channel Interrupt Enable Clear Register
CHINTENSETk - Channel Interrupt Enable Set Register
CHINTFk - Channel Interrupt Flag Register
CHSSAk - Channel Source Start Address
CHDSAk - Channel Destination Start Address
CHSSTRDk - Channel Source Cell Stride Size Register
CHDSTRDk - Channel Destination Cell Stride Size Register
CHXSIZk - Channel Transfer Size Register
CHPDATk - Channel Pattern Match Data
CHCTRLCRCk - Channel Control Crc
CHCRCDATk - Channel CRC/Checksum Data Register
CHNXTk - Channel Next Descriptor Address Pointer
CHLLCFGSTATk - Channel Linked List Configuration Status Register
CHSTATBCk - Channel Status Block Count Register
CHSTATCCk - Channel Status Cell Count Register
CHSTATk - Channel Status Register
So, the Channel Control Register A for Channel 5 (k=5) is CHCTRLA5.