43.2 Features

The following are key features of the ADC module:

Up to 12-bit resolution of the numerical output, signed or unsigned (Higher resolutions possible with oversampling).

  • Signed/Unsigned results
  • Left or Right aligned result
  • Fractional or integer results
  • Throughput rates (refer to the Electrical Specifications):
    Note:

    Assuming, GCLK_ADC = 50 MHz, TAD = 1/50 MHz = 20 ns.

    12-bit resolution: Up to 3.125 Msps

    10-bit resolution: Up to 3.571429 Msps

    8-bit resolution: Up to 4.166667 Msps

  • Maximum of 12 unique external analog input channels
    • VINP[11:0] ADC Module 0
  • Internal inputs:
    • Temperature Sensor internal analog channel AIN12
    • IVREF 1.2v, internal analog channel AIN13
    Note: The minimum sample rate for ADC is Ftpr >= 100 ksps.
  • ADC 12 single ended external analog inputs or up to three differential inputs plus 2 internal channels
  • Up to 16 trigger sources, off-chip hardware or on-chip hardware or software generated per analog input channel
  • Edge or level active triggering modes, generating single conversions or bursts of conversions
  • A scan trigger to start a scan cycle which can individually include or not include any of the analog inputs
  • Any of the 16 trigger sources or the scan triggers can be assigned to individual analog input channels
  • The scan trigger itself can select any of the 16 trigger sources as its own source
  • Programmable sampling time, CORCTRL.SAMC
  • Each analog input/channel output register can be read from a general dedicated output register (Write to the CORDYID and CHRDYID registers, then reads the CHRDYDATA register)
  • 16 sample deep FIFO supporting all channels
  • Digital Comparator for monitoring output values in relation to user-specified ADC result threshold
  • Digital filter, providing averaging/oversampling for increased noise immunity and are assignable to any analog input