51.32 Ethernet MAC (ETH) Electrical Specifications
AC CHARACTERISTICS | Standard
Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise
stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial | ||||||
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Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions |
MII Output AC TIMING Requirements | |||||||
ET_1 | tMDIOSU | MDIO Set-up Time | -32 | — | — | ns | VDDIO = 3.3V with CLOAD = 20 pF |
ET_3 | tMDIOHOLD | MDIO Hold Time | 0 | — | — | ns | |
ET_5 | tMDIOVAL | MDIO OUTPUT Valid Time | 36 | — | 40 | ns | |
MII RX AC TIMING Requirements | |||||||
ET_7 | tRXCLK | RXCLK Period | Note 1 | — | — | ns | VDDIO = 3.3V with CLOAD = 20 pF |
ET_9 | tRXCLKH | RXCLK High Time | tRXCLK / 2 | — | — | ns | |
ET_11 | tRXCLKL | RXCLK Low Time | tRXCLK / 2 | — | — | ns | |
ET_13 | tRXSU tRXERSU tRXDVSU | ERX[3:0], ERXER & ERXDV Set-up Time | 4 | — | — | ns | |
ET_15 | tRXHOLD tRXERHOLD tRXDVHOLD | ERX[3:0], ERXER & ERXDV Hold Time | 0 | — | — | ns | |
MII TX AC TIMING Requirements | |||||||
ET_17 | tTXCLK | TXCLK Period | Note 1 | — | — | ns | VDDIO = 3.3V with CLOAD = 20 pF |
ET_19 | tTXCLKH | TXCLK High Time | tTXCLK / 2 | — | — | ns | |
ET_21 | tTXCLKL | TXCLK Low Time | tTXCLK / 2 | — | — | ns | |
ET_23 | tTXCOLSU tTXCRSSU | TXCOL & TXCRS Set-up Time | 29 | — | — | ns | |
ET_25 | tTXCOLHOLD tTXCRSHOLD | TXCOL & TXCRS Hold Time | 9 | — | — | ns | |
ET_27 | tTX[3:0]VAL tTXERVAL tTXENVAL | TX[3:0], TXER & TXEN valid times | 9 | — | 11 | ns | — |
Note:
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AC CHARACTERISTICS | Standard
Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise
stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial | ||||||
---|---|---|---|---|---|---|---|
Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions |
RMII AC TIMING Requirements | |||||||
ET_29 | tREFCLK | Reference Clock Period | — | Note 1 | — | ns | VDDIO = 3.3V with CLOAD = 20 pF |
ET_31 | tREFCLKIH | Reference Clock High Time | — | tREFCLK / 2 | — | ns | |
ET_33 | tREFCLKIL | Reference Clock Low Time | — | tREFCLK / 2 | — | ns | |
ET_35 | REFCLKDC | Reference Clock Duty Cycle | — | 50 | — | % | |
ET_41 | tRX[1:0]SU tRXERSU | RXD[1:0], RXER Set-up time | 4 | — | — | ns | |
ET_43 | tRX[1:0]HOLD tRXERHOLD | RXD[1:0], RXER hold time | 0 | — | — | ns | |
ET_45 | tTX[1:0]VAL tTXENVAL | TX[1:0], TXEN valid time | 9 | — | 10 | ns | |
Note:
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