18.5 Peripheral Dependencies
| Peripheral
Name | Base Address | NVIC IRQ Index: Source | MCLK AHBx/APBx Clock Enable Mask Bit | GCLK Peripheral Channel
Clock Name:Register | PAC Peripheral Identifier
(PAC.WRCTRL.PERIDx) | EVSYS Generator
(EVSYS.CHANNELn.EVGENx) | Power Domain |
|---|---|---|---|---|---|---|---|
| OSCCTRL | 0x4400_C000 | 5 : XOSCFAIL, XOSCRDY, CLKFAIL 6 : DFLLRDY, DFLLLOCK, DFLLOVF, DFLLUNF, DFLLRCS, DFLLFAIL 7 : PLLLOCKR | MCLK.CLKMSK1[6] | GCLK_OSCCTRL_DFLL48: GCLK.PCHCTRL[0] GCLK_OSCCTRL_PLL: GCLK.PCHCTRL[1] | 6 : INTFLAGA[6] | 2:XOSC_FAIL | VDDREG,AVDD |
I/O Lines
The XOSC I/O lines are automatically configured when XOSC is enabled. There is no need for user configuration.
Power Management
The OSCCTRL can continue to operate in any sleep mode where the selected source clock is running. The OSCCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes.
For more information, refer to the Power Manager.
Clocks
The OSCCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller (GCLK). The available clock sources are: XOSC, DFLL48M, PLL, and FRACDIV.
The DFLL48M requires a reference clock (GCLK_DFLL48M_REF) from the GCLK. The control logic uses the oscillator output, which is asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details.
The PLL requires a reference clock (GCLK_PLL_REF) from the GCLK when the PLL reference selector PLLCTRL.REFSEL is set to GCLK.
The FRACDIV control logic uses the fractional divider output, which is asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details.
Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the OSCCTRL interrupts requires the interrupt controller to be configured first.
For more information, refer to the Nested Vector Interrupt Controller.
Events
The events are connected to the Event System. Using the events requires the Event System to be configured first. For more information, refer to the Event System (EVSYS).
Debug Operation
When the CPU is halted in Debug mode the OSCCTRL continues normal operation. If the OSCCTRL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers: The Interrupt Flag Status and Clear register (INTFLAG).
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger.
Analog Connections
The 4-48 MHz crystal must be connected between the XIN and XOUT pins, along with any required load capacitors.