33.12 Register Summary

For descriptions and definitions of both Register and bitfield properties, refer to Register Properties.

Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00 and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
OffsetNameBit Pos.76543210
0x00DIR7:0DIR[7:0]
15:8DIR[15:8]
23:16DIR[23:16]
31:24DIR[31:24]
0x04DIRCLR7:0DIRCLR[7:0]
15:8DIRCLR[15:8]
23:16DIRCLR[23:16]
31:24DIRCLR[31:24]
0x08DIRSET7:0DIRSET[7:0]
15:8DIRSET[15:8]
23:16DIRSET[23:16]
31:24DIRSET[31:24]
0x0CDIRTGL7:0DIRTGL[7:0]
15:8DIRTGL[15:8]
23:16DIRTGL[23:16]
31:24DIRTGL[31:24]
0x10OUT7:0OUT[7:0]
15:8OUT[15:8]
23:16OUT[23:16]
31:24OUT[31:24]
0x14OUTCLR7:0OUTCLR[7:0]
15:8OUTCLR[15:8]
23:16OUTCLR[23:16]
31:24OUTCLR[31:24]
0x18OUTSET7:0OUTSET[7:0]
15:8OUTSET[15:8]
23:16OUTSET[23:16]
31:24OUTSET[31:24]
0x1COUTTGL7:0OUTTGL[7:0]
15:8OUTTGL[15:8]
23:16OUTTGL[23:16]
31:24OUTTGL[31:24]
0x20IN7:0IN[7:0]
15:8IN[15:8]
23:16IN[23:16]
31:24IN[31:24]
0x24CTRL7:0SAMPLING[7:0]
15:8SAMPLING[15:8]
23:16SAMPLING[23:16]
31:24SAMPLING[31:24]
0x28WRCONFIG7:0PINMASK[7:0]
15:8PINMASK[15:8]
23:16  SLEWLIM[1:0]ODRAINPULLENINENPMUXEN
31:24HWSELWRPINCFG WRPMUXPMUX[3:0]
0x2CEVCTRL7:0PORTEI0EVACT0[1:0]PID0[4:0]
15:8PORTEI1EVACT1[1:0]PID1[4:0]
23:16PORTEI2EVACT2[1:0]PID2[4:0]
31:24PORTEI3EVACT3[1:0]PID3[4:0]
0x30PMUX07:0PMUXO[3:0]PMUXE[3:0]
...        
0x3FPMUX157:0PMUXO[3:0]PMUXE[3:0]
0x40PINCFG07:0  SLEWLIM[1:0]ODRAINPULLENINENPMUXEN
...        
0x5FPINCFG317:0  SLEWLIM[1:0]ODRAINPULLENINENPMUXEN