47.5 Peripheral Dependencies

Peripheral

Name

Base AddressNVIC IRQ Index: SourceMCLK AHBx/APBx

Clock Enable Mask Bit

GCLK Peripheral Channel

Clock Name:Register

PAC Peripheral Identifier

(PAC.WRCTRL.PERIDx)

EVSYS Users

(EVSYS.USERm)

EVSYS Generator

(EVSYS.CHANNELn.EVGENx)

DMA Trigger Index:Source

(DMAC.CHCTRLBk.TRIGx)

Power

Domain

TCC00x4481_800068 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS

69 : MC0

70 : MC1

71 : MC2

72 : MC3

73 : MC4

74 : MC5

MCLK.CLKMSK2[11]GCLK_TCC0 : GCLK.PCHCTRL[23]3230 : EV0

31 : EV1

32 : MC0

33 : MC1

34 : MC2

35 : MC3

36 : MC4

37 : MC5

50 : OVF

51 : TRG

52 : CNT

53 : MC0

54 : MC1

55 : MC2

56 : MC3

57 : MC4

58 : MC5

13 : OVF

14 : MC0

15 : MC1

16 : MC2

17 : MC3

18 : MC4

19 : MC5

VDDCORE_SW
TCC10x4481_A00075 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS

76 : MC0

77 : MC1

78 : MC2

79 : MC3

80 : MC4

81 : MC5

MCLK.CLKMSK2[12]GCLK_TCC1 : GCLK.PCHCTRL[23]3338 : EV0

39 : EV1

40 : MC0

41 : MC1

42 : MC2

43 : MC3

44 : MC4

45 : MC5

59 : OVF

60 : TRG

61 : CNT

62 : MC0

63 : MC1

64 : MC2

65 : MC3

66 : MC4

67 : MC5

20 : OVF

21 : MC0

22 : MC1

23 : MC2

24 : MC3

25 : MC4

26 : MC5

VDDCORE_SW
TCC20x4481_C00082 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS

83 : MC_0

84 : MC_1

85 : MC_2

86 : MC_3

87 : MC_4

88 : MC_5

MCLK.CLKMSK2[13]GCLK_TCC2 : GCLK.PCHCTRL[24]3446 : EV0

47 : EV1

48 : MC0

49 : MC1

50 : MC2

51 : MC3

52 : MC4

53 : MC5

68 : OVF

69 : TRG

70 : CNT

71 : MC0

72 : MC1

73 : MC2

74 : MC3

75 : MC4

76 : MC5

27 : OVF

28 : MC0

29 : MC1

30 : MC2

31 : MC3

32 : MC4

33 : MC5

VDDCORE_SW
TCC30x4481_E00089 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS

90 : MC0

91 : MC1

92 : MC2

93 : MC3

94 : MC4

95 : MC5

MCLK.CLKMSK2[14]GCLK_TCC3 : GCLK.PCHCTRL[24]3554 : EV0

55 : EV1

56 : MC0

57 : MC1

58 : MC2

59 : MC3

60 : MC4

61 : MC5

77 : OVF

78 : TRG

79 : CNT

80 : MC0

81 : MC1

82 : MC2

83 : MC3

84 : MC4

85 : MC5

34 : OVF

35 : MC0

36 : MC1

37 : MC2

38 : MC3

39 : MC4

40 : MC5

VDDCORE_SW
TCC40x4500_8000120 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS

121 : MC0

122 : MC1

MCLK.CLKMSK3[4]GCLK_TCC4 : GCLK.PCHCTRL[29]4062 : EV0

63 : EV1

64 : MC0

65 : MC1

86 : OVF

87 : TRG

88 : CNT

89 : MC0

90 : MC1

49 : OVF

50 : MC0

51 : MC1

VDDCORE_SW
TCC50x4500_A000123 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS

124 : MC0

125 : MC1

MCLK.CLKMSK3[5]GCLK_TCC5 : GCLK.PCHCTRL[30]4166 : EV0

67 : EV1

68 : MC0

69 : MC1

91 : OVF

92 : TRG

93 : CNT

94 : MC0

95 : MC1

51 : OVF

52 : MC0

53 : MC1

VDDCORE_SW
TCC60x4500_C000126 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS

127 : MC0

128 : MC1

MCLK.CLKMSK3[6]GCLK_TCC6 : GCLK.PCHCTRL[31]4270 : EV0

71 : EV1

72 : MC0

73 : MC1

96 : OVF

97 : TRG

98 : CNT

99 : MC0

100 : MC1

54 : OVF

55 : MC0

56 : MC1

VDDCORE_SW
TCC70x4500_E000129 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS

130 : MC0

131 : MC1

MCLK.CLKMSK3[7]GCLK_TCC7 : GCLK.PCHCTRL[32]4374 : EV0

75 : EV1

76 : MC0

77 : MC1

101 : OVF

102 : TRG

103 : CNT

104 : MC0

105 : MC1

57 : OVF

58 : MC0

59 : MC1

VDDCORE_SW

I/O Lines

In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT).

References:
  • PORT - I/O Pin Controller

Clocks

The TCC bus clocks (CLK_TCCx_APB) where x is 0,1,2...7 is enabled by default, and can be enabled or disabled in the Main Clock (MCLK).

A generic clock (GCLK_TCCx) is required to clock the TCC. This clock must be configured and enabled in the Generic Clock Controller (GCLK) before using the TCC.

The generic clocks (GCLK_TCCx) are asynchronous to the bus clock (CLK_TCCx_APB). Due to this asynchronicity, writing certain registers will require synchronization between the clock domains. Refer to Synchronization for further details.

DMA

The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral the DMAC must be configured first. Refer to the DMAC – Direct Memory Access Controller chapter for details.

References:
  • DMAC

Interrupts

The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to the Nested Vector Interrupt Controller chapter for details.

References:
  • Nested Vector Interrupt Controller

Events

The events of this peripheral are connected to the Event System.

References:
  • EVSYS

Debug Operation

When the CPU is halted in Debug mode, this peripheral will halt normal operation. This peripheral can be forced to continue operation during debugging - refer to the Debug Control (DBGCTRL) register for details.

References:
  • TCC DBGCTRL Register

Register Access Protection

Registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following registers:

  • The Interrupt Flag register (INTFLAG)
  • The Status register (STATUS)
  • The Period and Period Buffer registers (PER, PERBUF)
  • The Compare/Capture and Compare/Capture Buffer registers (CCy, CCBUFy)
  • The Control Waveform register (WAVE)
  • The Pattern Generation Value and Pattern Generation Value Buffer registers (PATT, PATTBUF)
Note: Optional write protection is indicated by the "PAC Write Protection" property in the register description.

When the CPU is halted in Debug mode, write-protection is automatically disabled.

Write protection does not apply for accesses through an external debugger.