26.3 Block Diagram

As shown in the following figure, there are several power supply pins:

  • AVDD – Powers the Backup power domain as well as the ADC, Analog Comparator (AC), and the Peripheral Touch Controller (PTC).
  • VDDREG – Powers the internal regulators.
  • VDDIO – Powers I/O lines, an External Crystal Oscillator (XOSC), two charge pumps which support the Analog Comparator (AC) and the ADC on the device (ADC and PTC ADC). Most VDDIO pins also power the device's Flash panel through double bonding.
  • VDDUSB3V – Powers the USB ports on the device.
Figure 26-1. Supply Controller Block Diagram

Power domains (PDs) shown above are not independent. VDDCORE_*, VDDIO, and VDDREG share the same ground, VSS. However, AVDD has its own ground, AVSS. AVDD and VDDIO inputs must share the same supply, VDD.

The block diagram above also shows a variety of internally regulated power domains (VDDCORE PDs), nominally at 1.2V:

  • VDDCORE_BU: Powers the backup domain. It contains peripherals that remain powered in the Backup Sleep mode.
  • VDDCORE_SW: The main voltage domain for the CPU, bus, and most peripherals, which can be switch off (the _SW suffix).
  • VDDCORE_USB: Domain for the USB port.
  • VDDCORE_RAM: This domain is used to retain the devices SRAM.

The device’s internal main voltage regulators have three different modes, controlled by the Supply Controller (SUPC):

  • Active Run Mode: The default mode when the CPU and peripherals are running.
  • Idle/Standby: When the CPU and peripherals are in Standby mode.
  • Hibernate/Backup/Off Mode: When the chip is in Backup mode, the internal regulator is OFF, the VDDCORE_SW core power domain is OFF. The VDDCORE_BU backup domain is powered by the backup regulator (Low-Power Voltage Regulator for Core - LPVREGC).