43.7 Register Summary

For descriptions and definitions of both Register and bitfield properties, refer to Register Properties.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRLA	7:0	ONDEMAND	RUNSTDBY				ANAEN	ENABLE	SWRST
		15:8
		23:16
		31:24
0x04	CTRLB	7:0	SAMP	RQCNVRT			ADCHSEL[3:0]
		15:8	SWCNVEN				STRGEN	TRGSUSP	LSWTRG	GSWTRG
		23:16
		31:24
0x08	CTRLC	7:0	CNT[7:0]
		15:8	CNT[15:8]
		23:16
		31:24
0x0C ... 0x0F	Reserved
0x10	CTRLD	7:0
		15:8			CTLCKDIV[5:0]
		23:16				ANLEN				CHNEN
		31:24		VREFSEL[2:0]			WKUPCLKCNT[3:0]
0x14 ... 0x1F	Reserved
0x20	CONFIG[0].CORCTRL	7:0	SAMC[7:0]
		15:8	EIRQOVR	EIS[2:0]			SELRES[1:0]		SAMC[9:8]
		23:16		SCNRTDS	STRGLVL		STRGSRC[3:0]
		31:24		ADCDIV[6:0]
0x24	CONFIG[0].CHNCFG1	7:0	CHNCMPE7	CHNCMPE6	CHNCMPE5	CHNCMPE4	CHNCMPE3	CHNCMPE2	CHNCMPE1	CHNCMPE0
		15:8			CHNCMPE13	CHNCMPE12	CHNCMPE11	CHNCMPE10	CHNCMPE9	CHNCMPE8
		23:16	LVL7	LVL6	LVL5	LVL4	LVL3	LVL2	LVL1	LVL0
		31:24			LVL13	LVL12	LVL11	LVL10	LVL9	LVL8
0x28	CONFIG[0].CHNCFG2	7:0	CSS7	CSS6	CSS5	CSS4	CSS3	CSS2	CSS1	CSS0
		15:8		CSS14	CSS13	CSS12	CSS11	CSS10	CSS9	CSS8
		23:16	FRAC7	FRAC6	FRAC5	FRAC4	FRAC3	FRAC2	FRAC1	FRAC0
		31:24		FRAC14	FRAC13	FRAC12	FRAC11	FRAC10	FRAC9	FRAC8
0x2C	CONFIG[0].CHNCFG3	7:0				DIFF4		DIFF2		DIFF0
		15:8
		23:16	SIGN7	SIGN6	SIGN5	SIGN4	SIGN3	SIGN2	SIGN1	SIGN0
		31:24		SIGN14	SIGN13	SIGN12	SIGN11	SIGN10	SIGN9	SIGN8
0x30	CONFIG[0].CHNCFG4	7:0	TRGSRC1[3:0]				TRGSRC0[3:0]
		15:8	TRGSRC3[3:0]				TRGSRC2[3:0]
		23:16	TRGSRC5[3:0]				TRGSRC4[3:0]
		31:24	TRGSRC7[3:0]				TRGSRC6[3:0]
0x34	CONFIG[0].CHNCFG5	7:0	TRGSRC9[3:0]				TRGSRC8[3:0]
		15:8	TRGSRC11[3:0]				TRGSRC10[3:0]
		23:16	TRGSRC13[3:0]				TRGSRC12[3:0]
		31:24	TRGSRC15[3:0]				TRGSRC14[3:0]
0x38	CONFIG[0].CALCTRL	7:0	CALBITS[7:0]
		15:8	CALBITS[15:8]
		23:16	CALBITS[23:16]
		31:24	CALBITS[31:24]
0x3C	EVCTRL0	7:0			CMPEO	RESRDYEO	STARTINV			STARTEI
		15:8
		23:16
		31:24
0x40 ... 0xAF	Reserved
0xB0	CMPCTRL	7:0	ADCMPLO[7:0]
		15:8	IEBTWN	IELOHI	IELOLO	CMPEN	ADCMPLO[11:8]
		23:16	ADCMPHI[7:0]
		31:24			IEHIHI	IEHILO	ADCMPHI[11:8]
0xB4 ... 0xBF	Reserved
0xC0	FLTCTRL0	7:0				DATA16EN	FMODE	OVRSAM[2:0]
		15:8			FLTCHNID[3:0]					FLTEN
		23:16
		31:24
0xC4 ... 0xCF	Reserved
0xD0	CORCHDATAID	7:0					CHRDYID[3:0]
		15:8
		23:16
		31:24
0xD4	CHRDYDAT	7:0	CHRDYDAT[7:0]
		15:8	CHRDYDAT[15:8]
		23:16
		31:24					FRACT	SIGN	DIFF	LVL
0xD8	PFFDATA	7:0	PFFDATA[7:0]
		15:8	PFFDATA[15:8]
		23:16	PFFFRACT	PFFSIGN			PFFCHNID[3:0]
		31:24	PFFCNT[7:0]
0xDC ... 0xE3	Reserved
0xE4	PFFCTRL	7:0				PFFCR			PFFEN
		15:8
		23:16								PFFRDYDMA
		31:24
0xE8	SYNCBUSY	7:0						CTRLB	ENABLE	SWRST
		15:8
		23:16
		31:24
0xEC ... 0xFB	Reserved
0xFC	CTLINTENSET	7:0	VREFRDY	VREFUPD			CRRDY3	CRRDY2	CRRDY1	CRRDY0
		15:8					PFFHFUL	PFFRDY	PFFOVF	PFFUNF
		23:16
		31:24
0x0100	CTLINTENCLR	7:0	VREFRDY	VREFUPD						CRRDY
		15:8					PFFHFUL	PFFRDY	PFFOVF	PFFUNF
		23:16
		31:24
0x0104	CTLINTFLAG	7:0	VREFRDY	VREFUPD						CRRDY
		15:8					PFFHFUL	PFFRDY	PFFOVF	PFFUNF
		23:16
		31:24
0x0108 ... 0x011F	Reserved
0x0120	INTENCLR	7:0	SOVFL			CMPHIT
		15:8					EOSRDY	CHNERRC	FLTRDY	CHRDYC
		23:16	CHRDY[7:0]
		31:24	CHRDY[15:8]
0x0124	INTENSET	7:0	SOVFL			CMPHIT
		15:8					EOSRDY	CHNERRC	FLTRDY	CHRDYC
		23:16	CHRDY[7:0]
		31:24	CHRDY[15:8]
0x0128	INTFLAG	7:0	SOVFL			CMPHIT	CMPINTID[3:0]
		15:8	CRDYID[3:0]				EOSRDY	CHNERRC	FLTRDY	CHRDYC
		23:16	CHRDY[7:0]
		31:24	CHRDY[15:8]
0x012C ... 0x0167	Reserved
0x0168	DBGCTRL	7:0								DBGRUN
		15:8
		23:16
		31:24