51.6 MCU Standby Power

Table 51-9. CPU Standby Current Consumption DC Electrical Specifications
DC CHARACTERISTICS Standard Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsPower PinTyp. (1)Max.UnitsConditions
SPWR_1IDD_STANDBY (2)MCU IDD in STANDBY mode w/VDDCORE_x = 0.8V VDDIO = AVDD = 3.3V0.50.6mAFull System RAM retained (PM.STDBYCFG.RAMCFG = 0x0),

RAM Low Power mode disabled (PM.STDBYCFG.LPRAM = 0x0),

Voltage Regulators Low Voltage enabled (SUPC.VREGCTRL.LVSTDBY = 0x1)

SPWR_3VDDREG = 3.3V0.915mA
SPWR_5 VDDIO = AVDD = 3.3V0.50.6mA32 Kb System RAM retained (PM.STDBYCFG.RAMCFG = 0x1),

RAM Low Power mode disabled (PM.STDBYCFG.LPRAM = 0x0),

Voltage Regulators Low Voltage enabled (SUPC.VREGCTRL.LVSTDBY = 0x1)

SPWR_7VDDREG = 3.3V0.812.7mA
SPWR_9 VDDIO = AVDD = 3.3V0.50.6mAFull System RAM retained (PM.STDBYCFG.RAMCFG = 0x0),

RAM Low Power mode enabled (PM.STDBYCFG.LPRAM = 0x1),

Voltage Regulators Low Voltage enabled (SUPC.VREGCTRL.LVSTDBY = 0x1)

SPWR_11VDDREG = 3.3V0.812.9mA
SPWR_13MCU IDD in STANDBY mode w/VDDCORE_x = 1.2V VDDIO = AVDD = 3.3V0.50.7mAFull System RAM retained (PM.STDBYCFG.RAMCFG = 0x0),

RAM Low Power mode disabled (PM.STDBYCFG.LPRAM = 0x0),

Voltage Regulators Low Voltage disabled (SUPC.VREGCTRL.LVSTDBY = 0x0)

SPWR_15VDDREG = 3.3V1.441.7mA
SPWR_17 VDDIO = AVDD = 3.3V0.50.7mA32 Kb System RAM retained (PM.STDBYCFG.RAMCFG = 0x1),

RAM Low Power mode disabled (PM.STDBYCFG.LPRAM = 0x0),

Voltage Regulators Low Voltage disabled (SUPC.VREGCTRL.LVSTDBY = 0x0)

SPWR_19VDDREG = 3.3V1.334.7mA
SPWR_21 VDDIO = AVDD = 3.3V0.50.7mAFull System RAM retained (PM.STDBYCFG.RAMCFG = 0x0),

RAM Low Power mode enabled (PM.STDBYCFG.LPRAM = 0x1),

Voltage Regulators Low Voltage disabled (SUPC.VREGCTRL.LVSTDBY = 0x0)

SPWR_23VDDREG = 3.3V1.435.2mA
Note:
  1. Typical values at 25°C only.
  2. Conditions:
    • No peripheral modules are operating, unless specified (i.e. all peripherals inactive)
    • APB Peripheral bus clocks: default settings after reset
    • CMCC Cache disabled
    • MCU is running on Flash with automatic wait state
    • VREG_USB disabled
    • I/Os are inactive input mode with input trigger disabled
    • All clock generation sources disabled unless otherwise specified
    • WDT, CFD Clock Fail Detect disabled

Operating Conditions:

  • VDDIO = 3.3V
  • VDDCORE = 0.8V