13.7 RAM Properties

The following table shows the different access properties of the three RAM blocks, according the different modes described in the previous chapters.

Table 13-2. Access to RAM
Access ConditionDATA RAMTAG RAMMETADATARAM
CPU access when CMCC DISABLEDR/Wno R/W - hardfaultno R/W - hardfault
CPU access when CMCC ENABLED CACHE section configured: R/W(1)

TCM section configured: R/W

no R/W - hardfaultno R/W - hardfault
Debugger access when CMCC DISABLEDR/WR/WR/W
Debugger access when CMCC ENABLEDCACHE section configured: R/W(1)

TCM section configured: R/W

no R/Wno R/W
Note:
  1. A write operation in this zone can corrupt the coherency of the cache. An invalidate operation may be needed.