13.7 RAM Properties
The following table shows the different access properties of the three RAM blocks, according the different modes described in the previous chapters.
| Access Condition | DATA RAM | TAG RAM | METADATARAM |
|---|---|---|---|
| CPU access when CMCC DISABLED | R/W | no R/W - hardfault | no R/W - hardfault |
| CPU access when CMCC ENABLED | CACHE section
configured: R/W(1) TCM section configured: R/W | no R/W - hardfault | no R/W - hardfault |
| Debugger access when CMCC DISABLED | R/W | R/W | R/W |
| Debugger access when CMCC ENABLED | CACHE section
configured: R/W(1) TCM section configured: R/W | no R/W | no R/W |
Note:
- A write operation in this zone can corrupt the coherency of the cache. An invalidate operation may be needed.