51.35 Position Decoder (PDEC) Electrical Specifications
AC CHARACTERISTICS | Standard
Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise
stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial | ||||||
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Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions |
PDEC_1 | TtPH | TPCK high time | 2/fGCLK_PDEC | — | — | µs | VDDIOx(min) -to- VDDIOx(max) |
PDEC_3 | TtPL | TPCK low time | 2/fGCLK_PDEC | — | — | µs | |
PDEC_5 | TtPP | TPCK input period | 4/fGCLK_PDEC | — | — | µs | |
PDEC_7 | TCKEXTDLY | Delay from External TxCK Clock Edge to counter Increment | — | — | 4/fGCLK_PDEC | µs | |
PDEC_11 | TPDH | Position Decoder Input High Time | 4/fGCLK_PDEC | — | — | µs | |
PDEC_13 | TPDL | Position Decoder Input Low Time | 4/fGCLK_PDEC | — | — | µs | |
PDEC_15 | TPDIN | Position Decoder Input Period | 8/fGCLK_PDEC | — | — | µs | |
PDEC_21 | TPDFH | Filter Time to Recognize High, with Digital Filter | 4/fGCLK_PDEC | — | — | µs | |
PDEC_23 | TPDFL | Filter Time to Recognize Low, with Digital Filter | 4/fGCLK_PDEC | — | — | µs | |
PDEC_24 | fGCLK_PDEC | GCLK_PDEC | — | — | FCLK_35A | MHz |