31.7.1.6 Interrupts

There are multiple interrupt conditions that are detected within the ETH. The conditions are ORed to make multiple interrupts. Each queue has its own interrupt vector. There are 6 interrupt lines connected to the NVIC correspondence to each queue. On receipt of the interrupt signal, the CPU enters the interrupt handler. Refer to the NVIC chapter to find more information about ETH Queue Interrupts.

At reset all interrupts are disabled. To enable an interrupt, write to Interrupt Enable register with the pertinent interrupt bit set to 1. To disable an interrupt, write to Interrupt Disable register with the pertinent interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read Interrupt Mask register. If the bit is set to 1, the interrupt is disabled.