23.8.3 Configuration A
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CFGA |
| Offset: | 0x02 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection, Enable-protected |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DIVREF | MRSEL | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| REFNUM[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – DIVREF Divide Reference Clock
Divides the reference clock by 8
| Value | Description |
|---|---|
| 0 | The reference clock is divided by 1. |
| 1 | The reference clock is divided by 8. |
Bit 8 – MRSEL Frequency Meter Clock Measure Selection
| Value | Description |
|---|---|
| 0 | Select GCLK_FREQM_MSR as FREQM clock to measure |
| 1 | Select GCLK_ 0 as FREQM clock to measure |
Bits 7:0 – REFNUM[7:0] Number of Reference Clock Cycles
Selects the duration of a measurement in number of CLK_FREQM_REF cycles.
Note: The measurement reference period must be longer than 4 APB
clock periods.