34.7.2 Features
SERCOM SPI includes the following features:
- Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
- One-level transmit buffer, two-level receive buffer
- Supports all four SPI modes of operation
- Single data direction operation allows alternate function on MISO or MOSI pin
- Selectable LSB- or MSB-first data transfer
- Can be used with DMA
- 32-bit Extension for better system bus utilization
- Framed SPI protocol support in both Host and Client operating mode, with hardware controlled FSYNC
- Up to 16-bytes internal FIFO
- Host operation:
- Serial clock speed, fSCK=1/tSCK(1)
- 8-bit clock generator
- Hardware controlled SS
- Optional inter-character spacing
- Client Operation:
- Serial clock speed, fSCK=1/tSSCK(1)
- Optional 8-bit address match operation
- Operation in all sleep modes
- Wake on SS transition
Note:
- For tSCK and tSSCK values, refer to SPI Timing Characteristics.