25.7.1 Overview

The Direct Memory Access (DMA) Controller can transfer data between memories and peripheral at a high data transfer rate without CPU intervention.

This module provides up to 12 independent DMA channels. Each channel can be uniquely configured to transfer data from a source location to a destination location on a trigger event. Channels share access to the system bus through a Read and Write port as shown in the block diagram.

The block diagram shows the major components of the DMA which include the read port (DMAR), the write port (DMAW), the channel FIFOs, the FSM (DMA_TOP_FSM) which includes the link list parser (LINK_PARSER), the CRC engine, and the SFR registers.

The read port allows the DMA to load descriptors and read source data. Channels arbitrate for access to the read port based on both a natural order priority and a software programmable priority.

The write port allows the DMA to write data to the destination address. As with the read port, channels arbitrate for access to the write port based on natural order priority and software programmable priority.

The channel FIFO provides storage for data that is in transit from source to destination.

The FSM manages configuration updates for each channel, trigger events, arbitration, linked list parsing, and interrupts. The FSM handles configuration of the CRC engine when processing source data from one channel to another.