18.7.19 PLL Synchronization Busy

Table 18-23. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	SYNCBUSY
Offset:	0x78
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
		FRACDIV0	DFLLMUL	DFLLDIFF	DFLLTUNE	DFLLCTRLB	DFLLENABLE
Access		R	R	R	R	R	R
Reset		0	0	0	0	0	0

Bit 6 – FRACDIV0 FRACDIV0 Synchronization Busy

This bit is cleared when the synchronization of FRACDIV0 register between the clock domains is complete. This bit is set when the synchronization of FRACDIV0 register between clock domains is started.

Note: The FRACDIV0 synchronization only applies for write operations.

Bit 5 – DFLLMUL DFLLMUL Synchronization Busy

This bit is cleared when the synchronization of DFLLMUL register between the clock domains is complete. This bit is set when the synchronization of DFLLMUL register between clock domains is started.

Note: The DFLLMUL synchronization only applies for write operations.

Bit 4 – DFLLDIFF DFLLDIFF Synchronization Busy

This bit is cleared when the synchronization of DFLLDIFF register between the clock domains is complete. This bit is set when the synchronization of DFLLDIFF register between clock domains is started.

Note: The DFLLDIFF synchronization only applies for read operations.

Bit 3 – DFLLTUNE DFLLTUNE Synchronization Busy

This bit is cleared when the synchronization of DFLLTUNE register between the clock domains is complete. This bit is set when the synchronization of DFLLTUNE register between clock domains is started.

Note: The DFLLTUNE synchronization applies for read and write operations.

Bit 2 – DFLLCTRLB DFLLCTRLB Synchronization Busy

This bit is cleared when the synchronization of DFLLCTRLB register between the clock domains is complete. This bit is set when the synchronization of DFLLCTRLB register between clock domains is started.

Note: The DFLLCTRLB synchronization only applies for write operations.

Bit 1 – DFLLENABLE DFLL48M Enable Synchronization Busy

This bit is cleared when the synchronization of the DFLLCTRLA.ENABLE register bit between the clock domains is complete.

Note: This bit is set when the synchronization of the DFLLCTRLA.ENABLE register bit between clock domains is started.