10.3.2 NVIC Interrupt Line Mapping
Each of the interrupt lines is connected to a single peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.
An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a '1' to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register and disabled by writing '1' to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTEN- CLR) register.
An interrupt request is generated from the peripheral when the interrupt flag is set when the corresponding interrupt is enabled.
An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/ CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.
| NVIC Interrupt Mapping | |
|---|---|
| Module | Interrupt Index: Source |
| FCR - PFM READ Controller | 0: ECERR |
| 1 : FAULT or CRCERR FLT, CRC | |
| FCW - PFM WRITE Controller | 2 : FCW MAIN |
| PM - Power Manager | 3 : SLEEPRDY |
| SUPC - Supply Controller | 4 : LVDET, LVDRDY, BORVDDUSB_0, ADDVREGRDY_0 |
| OSCCTRL - Oscillators Control | 5 : XOSCFAIL, XOSCRDY, CLKFAIL |
| 6 : DFLLRDY, DFLLLOCK, DFLLOVF, DFLLUNF, DFLLRCS, DFLLFAIL | |
| 7 : PLLLOCKR | |
| OSC32KCTRL- 32kHz Oscillators Control | 8 : XOSC32KRDY, XOSC32KFAIL |
| MCLK - Main Clock | 9 : CKRDY |
| FREQM - Frequency Meter | 10 : DONE, WINMON |
| WDT - Watchdog Timer | 11 : EW |
| RTC - Real-Time Counter | 12 : PER_0, PER_1, PER_2, PER_3, PER_4, PER_5, PER_6, PER_7, CMP_0, CMP_1, CMP_2, CMP_3, TAMPER, OVF |
| EIC - External Interrupt Controller | NMI : EXTINT_NMI |
| 13 : EXTINT_0 | |
| 14 : EXTINT_1 | |
| 15 : EXTINT_2 | |
| 16 : EXTINT_3 | |
| 17 : EXTINT_4 | |
| 18 : EXTINT_5 | |
| 19 : EXTINT_6 | |
| 20 : EXTINT_7 | |
| 21 : EXTINT_8 | |
| 22 : EXTINT_9 | |
| 23 : EXTINT_10 | |
| 24 : EXTINT_11 | |
| 25 : EXTINT_12 | |
| 26 : EXTINT_13 | |
| 27 : EXTINT_14 | |
| 28 : EXTINT_15 | |
| 29 : NSCHK | |
| PAC - Peripheral Access Controller | 30 : ERR |
| TRAM - Trust RAM | 31 : ERR, DRP |
| PORT - Port A/B/C/D | 32 : NSCHK_0, NSCHK_1, NSCHK_2, NSCHK_3 |
| DMA0 - Direct Memory Access Controller 0 | 33 : Priority 0 |
| 34 : Priority 1 | |
| 35 : Priority 2 | |
| DMA1 - Direct Memory Access Controller 1 | 36 : Priority 0 |
| 37 : Priority 1 | |
| HMATRIX | 38 : CMCC, PRM HMATRIX |
| EVSYS - Event System Interface | 39 : EVD_0, OVR_0 |
| 40 : EVD_1, OVR_1 | |
| 41 : EVD_2, OVR_2 | |
| 42 : EVD_3, OVR_3 | |
| 43 : EVD_4, OVR_4, EVD_5, OVR_5, EVD_6, OVR_6, EVD_7, OVR_7, EVD_8, OVR_8, EVD_9, OVR_9, EVD_10, OVR_10, EVD_11, OVR_11, NSCHK | |
| SERCOM0 - Serial Communication Interface 0 | 44 : ERROR, RXBRK |
| 45 : DRE/PREC | |
| 46 : TXC/AMATCH | |
| 47 : RXC/DRDY | |
| 48: RXS/SSL/TXFE | |
| 49 : CTSIC/RXFF | |
| SERCOM1 - Serial Communication Interface 1 | 50 : ERROR, RXBRK |
| 51 : DRE/PREC | |
| 52 : TXC/AMATCH | |
| 53 : RXC/DRDY | |
| 54 : RXS/SSL/TXFE | |
| 55 : CTSIC/RXFF | |
| SERCOM2 - Serial Communication Interface 2 | 56 : ERROR, RXBRK |
| 57 : DRE/PREC | |
| 58 : TXC/AMATCH | |
| 59 : RXC/DRDY | |
| 60 : RXS/SSL/TXFE | |
| 61 : CTSIC/RXFF | |
| SERCOM3 - Serial Communication Interface 3 | 62 : ERROR, RXBRK |
| 63 : DRE/PREC | |
| 64 : TXC/AMATCH | |
| 65 : RXC/DRDY | |
| 66 : RXS/SSL/TXFE | |
| 67 : CTSIC/RXFF | |
| TCC0 - Timer Counter Control 0 | 68 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS |
| 69 : MC_0 | |
| 70 : MC_1 | |
| 71 : MC_2 | |
| 72 : MC_3 | |
| 73 : MC_4 | |
| 74 : MC_5 | |
| TCC1 - Timer Counter Control 1 | 75 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS |
| 76 : MC_0 | |
| 77 : MC_1 | |
| 78 : MC_2 | |
| 79 : MC_3 | |
| 80 : MC_4 | |
| 81 : MC_5 | |
| TCC2 - Timer Counter Control 2 | 82 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS |
| 83 : MC_0 | |
| 84 : MC_1 | |
| 85 : MC_2 | |
| 86 : MC_3 | |
| 87 : MC_4 | |
| 88 : MC_5 | |
| TCC3 - Timer Counter Control 3 | 89 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS |
| 90 : MC_0 | |
| 91 : MC_1 | |
| 92 : MC_2 | |
| 93 : MC_3 | |
| 94 : MC_4 | |
| 95 : MC_5 | |
| SERCOM4 - Serial Communication Interface 4 | 96 : ERROR, RXBRK |
| 97 : DRE/PREC | |
| 98 : TXC/AMATCH | |
| 99 : RXC/DRDY | |
| 100 : RXS/SSL/TXFE | |
| 101 : CTSIC/RXFF | |
| SERCOM5 - Serial Communication Interface 5 | 102 : ERROR, RXBRK |
| 103 : DRE/PREC | |
| 104 : TXC/AMATCH | |
| 105 : RXC/DRDY | |
| 106 : RXS/SSL/TXFE | |
| 107 : CTSIC/RXFF | |
| SERCOM6 - Serial Communication Interface 6 | 108 : ERROR, RXBRK |
| 109 : DRE/PREC | |
| 110 : TXC/AMATCH | |
| 111 : RXC/DRDY | |
| 112 : RXS/SSL/TXFE | |
| 113 : CTSIC/RXFF | |
| SERCOM7 - Serial Communication Interface 7 | 114 : ERROR, RXBRK |
| 115 : DRE/PREC | |
| 116 : TXC/AMATCH | |
| 117 : RXC/DRDY | |
| 118 : RXS/SSL/TXFE | |
| 119 : CTSIC/RXFF | |
| TCC4 - Timer Counter Control 4 | 120 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS |
| 121 : MC_0 | |
| 122 : MC_1 | |
| TCC5 - Timer Counter Control 5 | 123 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS |
| 124 : MC_0 | |
| 125 : MC_1 | |
| TCC6 - Timer Counter Control 6 | 126 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS |
| 127 : MC_0 | |
| 128 : MC_1 | |
| TCC7 - Timer Counter Control 7 | 129 : CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS |
| 130 : MC_0 | |
| 131 : MC_1 | |
| ADC - Analog Digital Controller | 132 : ADC Global Interrupt, 133 : ADC Core 0 Interrupt, 134-137 : Reserved |
| AC - Analog Comparator | 138 : COMP_0, COMP_1, WIN_0 |
| PTC - Peripheral Touch | 139 : EOC, WCOMP, ACRRDY |
| SPI_IXS - AUDIO SPI IxS | 140 : SPI_IXS |
| PCC - Parallal Capture Controller | 141 : PCC |
| PDEC | 142 : DIR, ERR, MC_0, MC_1, OVF, VLC |
| CAN0 - Control Area Network | 143 : LINE_0, LINE_1, ERROR |
| CAN1 - Control Area Network | 144 : LINE_0, LINE_1, ERROR |
| ETH - Ethernet MAC | 145 : Q_0 |
| SQI - Quad SPI interface | 146 : SQI |
| TRNG - True Random Generator | 147 : IS0 |
| SDMMC0- SD/MMC Host Controller 0 | 148 : LINE, TIMER |
| SDMMC1 - SD/MMC Host Controller 1 | 149 : LINE, TIMER |
| USBFS - Full-Speed Universal Serial Bus | 150 : EORSM_DNRSM, EORST_RST, LPM_DCONN, LPMSUSP_DDISC, MSOF, RAMACER, RXSTP_TXSTP[0:7], STALL0_STALL[0:7], STALL1[0:7], SUSPEND, TRFAIL0_TRFAIL[0:7], TRFAIL1_PERR[0:7], UPRSM, WAKEUP |
| 151 : SOF_HSOF | |
| 152 : TRCPT0[0:7] | |
| 153 : TRCPT1[0:7] | |
| USBHS - High Speed Universal Serial Bus | 154 : USBHS |
| HSM | 155 : ERROR, TAMPER |
| 156 : TXINT | |
| 157 : RXINT | |