40.6 Peripheral Dependencies
| Peripheral
Name | Base Address | NVIC IRQ
Index:Source | MCLK AHBx/APBx Clock Enable Mask Bit | GCLK Peripheral Channel Clock Name : Register | PAC Peripheral ID
(PAC.WRCTRL.PERIDx) | Power Domain |
|---|---|---|---|---|---|---|
| SDMMC0 | 0x4502_6000 | 148 : LINE, TIMER | MCLK.CLKMSK0[17] |
GCLK_SDMMC0_SLOW : GCLK.PCHCTRL[18] GCLK_SDMMC0_CORE : GCLK.PCHCTRL[44] | 55 | VDDREG |
| SDMMC1 | 0x4502_8000 | 149 : LINE, TIMER | MCLK.CLKMSK0[18] |
GCLK_SDMMC1_SLOW : GCLK.PCHCTRL[18] GCLK_SDMMC1_CORE : GCLK.PCHCTRL[45] | 56 | VDDREG |
I/O Lines
In order to use the I/O lines, the I/O pins must be configured using the IO Pin Controller (PORT).
Clocks
The peripheral is using two generic clocks and one bus clock.
The clock for the SDHC bus interface (CLK AHB SDHC) is enabled and disabled by the Main Clock Controller. The default state of CLK AHB SDHC can be found in the Peripheral Clock Masking section.
The two generic clocks are:
- The core clock GCLK SDHCx is required to clock the SDHC core.
- The slow clock GCLK SDHCx SLOW is only required for certain functions. When this clock is required, GCLK SDHCx must be enabled.
These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SDHC. The generic clocks are asynchronous to the user interface clock (CLK SDHCx AHB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains.
DMA
The SDHC has a built-in Direct Memory Access (DMA) and will read/write data to/from the system RAM when a SDHC transaction takes place. No CPU or DMA Controller (DMAC) resources are required.
Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first.