28.7.1 Reset Cause

Note: Only one bit is set at any one time. This register only reflects the last event.

Table 28-3. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	RCAUSE
Offset:	0x0000
Reset:	0x0000
Property:	–


Bit	15	14	13	12	11	10	9	8
							LOCKUP	BACKUP
Access							R	R
Reset							0	0


Bit	7	6	5	4	3	2	1	0
	SYST	WDT	EXT	BORVDDIO	BORVDDA	BORVDDREG	PORCORE	POR
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 9 – LOCKUP Lockup Reset

CPU has entered lockup state (for details, refer to the “Arm® Cortex™ Technical Reference Manual” available at www.arm.com).

Bit 8 – BACKUP Backup Reset

Reset cause when leaving Backup or Hibernate mode due to wake event (RTC).

Bit 7 – SYST System Reset Request

Reset generated by a System Reset Request by the CPU by asserting the SYSRESETREQ bit located in the Reset Control register of the CPU (for details, refer to the “Arm® Cortex™ Technical Reference Manual” available at www.arm.com).