29.7.6 Interrupt Enable Clear
Note:
- Access to this register is limited to 32-bit width. Byte level access is not allowed.
- Reserved bits must always be written as ‘0’.
- Interrupt flags must be cleared and then read back to confirm the clear before exiting the ISR to avoid double interrupts.
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Important: On devices with security
attribution Non-Secure accesses, read and write accesses (RW*) are allowed only if
the external interrupt x (EXTINTx) is set as Non-Secure in the NONSEC register
(NONSEC.EXTINTx bit).
Name: | INTENCLR |
Offset: | 0x0C |
Reset: | 0x00000000 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
NSCHK | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
EXTINT[15:8] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
EXTINT[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – NSCHK Non-secure Check Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the NSCHK Interrupt Enable bit. For devices without TrustZone support, this location is reserved.
Value | Description |
---|---|
0 | The external interrupt EIC_EXTINTx is disabled. |
1 | The external interrupt EIC_EXTINTx is enabled. |
Bits 15:0 – EXTINT[15:0] External Interrupt Enable
The bit x of EXTINT enables the interrupt associated with the EIC_EXTINTx pin.
Writing a '0' to bit x has no effect.
Writing a '1' to bit x will clear the External Interrupt Enable bit x, which disables the external interrupt EIC_EXTINTx pin(s).
Value | Description |
---|---|
0 | The external interrupt EIC_EXTINTx is disabled. |
1 | The external interrupt EIC_EXTINTx is enabled. |