38.5 Peripheral Dependencies

Peripheral

Name

Base

Address

NVIC IRQ

Index:Source

MCLK AHBx/APBx

Clock Enable Mask Bit

GCLK

Peripheral Channel

Clock Name : Register

PAC Peripheral ID

(PAC.WRCTRL.PERIDx)

DMA Trigger

Index:Source

(DMAC.CHCTRLBk.TRIGx)

Power

Domain

CAN00x4501_E000

143 : LINE0,

LINE1,

ERROR

MCLK.CLKMSK0[13]GCLK_CAN0 : GCLK.PCHCTRL[39]5168 : DEBUGVDDREG
CAN10x4502_0000144:

LINE0,

LINE1,

ERROR

MCLK.CLKMSK0[14]GCLK_CAN1 : GCLK.PCHCTRL[40]5269 : DEBUGVDDREG
Note: In order to use this peripheral, other parts of the system must be configured correctly, as described below.

I/O Lines

Using the CAN’s I/O lines requires the I/O pins to be configured.

References:

PORT - I/O Pin Controller

Clocks

An AHB clock CLK_CANx_AHB (where x = 0, 1) is required to clock the CAN. The CAN AHB BUS interface clocks are enabled by default on reset. This clock can be configured in the Main Clock peripheral (MCLK) before using the CAN, and the default state of CLK_CANx_AHB can be found in the AHBMASK register of the MCLK (Main Clock Controller) module.

A generic clock GCLK_CANx (where x = 0, 1) is required to clock the CAN. This clock must be configured and enabled in the generic clock controller before using the CAN.

This generic clock is asynchronous to the bus clock (CLK_CANx_AHB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains.

References:

Peripheral Clock Masking

Generic Clock Controller - GCLK

DMA

The CAN has a built-in Direct Memory Access (DMA) and will read/write data to/from the system RAM when a CAN transaction takes place. No CPU or DMA Controller (DMAC) resources are required.

The DMAC can be used for debug messages functionality.