13.2 Features

The following are key features of the Cortex-M Cache Controller:

  • Physically addressed and physically tagged
  • L1 data and instruction cache set to 4 KB
  • L1 cache line size set to 16 Bytes
  • L1 cache integrates 32-bit bus host interface
  • Unified 4-Way set associative cache architecture
  • Lock-Down feature, which allows cached to be locked per way
  • Write through cache operations, read allocate
  • Configurable as data and instruction Tightly Coupled Memory (TCM)
  • Round Robin victim selection policy
  • Event Monitoring with one programmable 32-bit counter
  • Cache Interface includes cache maintenance operations registers