17.3.7 Synchronization Delay

The synchronization will delay write and read accesses by a certain amount. This delay D is within the range of:

5×P_GCLK + 2×P_APB < D < 6×P_GCLK + 3×P_APB

Where P_GCLK is the period of the generic clock and P_APB is the period of the peripheral bus clock. A normal peripheral bus register access duration is 2×P_APB.