19.6.3.1 Enabling a Peripheral Clock

Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and selected as source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral Channel Control register (PCHCTRLm.GEN). Any available Generator can be selected as clock source for each Peripheral Channel.

When a Generator has been selected, the peripheral clock is enabled by setting the Channel Enable bit in the Peripheral Channel Control register, PCHCTRLm.CHEN = 1. The PCHCTRLm.CHEN bit must be synchronized to the generic clock domain. PCHCTRLm.CHEN will continue to read as its previous state until the synchronization is complete.

Table 19-2. PCHCTRL (Index) GCLK Mapping
Target DestinationGCLK NamePCHCTRL (Index)
OSCCTRLGCLK_OSCCTRL_DFLL480
GCLK_OSCCTRL_PLL1
FREQMGCLK_FREQM_MSR02
GCLK_FREQM_MSR13
GCLK_FREQM_REF4
EICGCLK_EIC5
EVSTSGCLK_EVSYS_CH06
GCLK_EVSYS_CH17
GCLK_EVSYS_CH28
GCLK_EVSYS_CH39
GCLK_EVSYS_CH410
GCLK_EVSYS_CH511
GCLK_EVSYS_CH612
GCLK_EVSYS_CH713
GCLK_EVSYS_CH814
GCLK_EVSYS_CH915
GCLK_EVSYS_CH1016
GCLK_EVSYS_CH1117
SERCOMm, m = 0…7 SDMMCn, n = 0,1GCLK_SERCOMm_SLOW, m = 0…7 SDMMCn_SLOW, n=0,118
SERCOM0GCLK_SERCOM0_CORE19
SERCOM1GCLK_SERCOM1_CORE20
SERCOM2GCLK_SERCOM2_CORE21
SERCOM3GCLK_SERCOM3_CORE22
TCC0,TCC1GLCK_TCC0, GCLK_TCC123
TCC2,TCC3GLCK_TCC2, GCLK_TCC324
SERCOM4GCLK_SERCOM4_CORE25
SERCOM5GCLK_SERCOM5_CORE26
SERCOM6GCLK_SERCOM6_CORE27
SERCOM7GCLK_SERCOM7_CORE28
TCC4GCLK_TCC429
TCC5GCLK_TCC530
TCC6GCLK_TCC631
TCC7GCLK_TCC732
ADCGCLK_ADC33
ACGCLK_AC34
PTCGCLK_PTC35
SPI_IXSGCLK_SPI_IXS36
CCLGCLK_CCL37
PDECGCLK_PDEC38
CAN0GCLK_CAN039
CAN1GCLK_CAN140
ETHGCLK_ETH_TX41
GCLK_ETH_TSU42
SQIGCLK_SQI43
SDMMC0GLCK_SDMMC044
SDMMC1GLCK_SDMMC145
USBGCLK_USB46
CPU0GCLK_CPU0_TRACE47