19.6.3.1 Enabling a Peripheral Clock
Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and selected as source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral Channel Control register (PCHCTRLm.GEN). Any available Generator can be selected as clock source for each Peripheral Channel.
When a Generator has been selected, the peripheral clock is enabled by setting the Channel Enable bit in the Peripheral Channel Control register, PCHCTRLm.CHEN = 1. The PCHCTRLm.CHEN bit must be synchronized to the generic clock domain. PCHCTRLm.CHEN will continue to read as its previous state until the synchronization is complete.
Target Destination | GCLK Name | PCHCTRL (Index) |
---|---|---|
OSCCTRL | GCLK_OSCCTRL_DFLL48 | 0 |
GCLK_OSCCTRL_PLL | 1 | |
FREQM | GCLK_FREQM_MSR0 | 2 |
GCLK_FREQM_MSR1 | 3 | |
GCLK_FREQM_REF | 4 | |
EIC | GCLK_EIC | 5 |
EVSTS | GCLK_EVSYS_CH0 | 6 |
GCLK_EVSYS_CH1 | 7 | |
GCLK_EVSYS_CH2 | 8 | |
GCLK_EVSYS_CH3 | 9 | |
GCLK_EVSYS_CH4 | 10 | |
GCLK_EVSYS_CH5 | 11 | |
GCLK_EVSYS_CH6 | 12 | |
GCLK_EVSYS_CH7 | 13 | |
GCLK_EVSYS_CH8 | 14 | |
GCLK_EVSYS_CH9 | 15 | |
GCLK_EVSYS_CH10 | 16 | |
GCLK_EVSYS_CH11 | 17 | |
SERCOMm, m = 0…7 SDMMCn, n = 0,1 | GCLK_SERCOMm_SLOW, m = 0…7 SDMMCn_SLOW, n=0,1 | 18 |
SERCOM0 | GCLK_SERCOM0_CORE | 19 |
SERCOM1 | GCLK_SERCOM1_CORE | 20 |
SERCOM2 | GCLK_SERCOM2_CORE | 21 |
SERCOM3 | GCLK_SERCOM3_CORE | 22 |
TCC0,TCC1 | GLCK_TCC0, GCLK_TCC1 | 23 |
TCC2,TCC3 | GLCK_TCC2, GCLK_TCC3 | 24 |
SERCOM4 | GCLK_SERCOM4_CORE | 25 |
SERCOM5 | GCLK_SERCOM5_CORE | 26 |
SERCOM6 | GCLK_SERCOM6_CORE | 27 |
SERCOM7 | GCLK_SERCOM7_CORE | 28 |
TCC4 | GCLK_TCC4 | 29 |
TCC5 | GCLK_TCC5 | 30 |
TCC6 | GCLK_TCC6 | 31 |
TCC7 | GCLK_TCC7 | 32 |
ADC | GCLK_ADC | 33 |
AC | GCLK_AC | 34 |
PTC | GCLK_PTC | 35 |
SPI_IXS | GCLK_SPI_IXS | 36 |
CCL | GCLK_CCL | 37 |
PDEC | GCLK_PDEC | 38 |
CAN0 | GCLK_CAN0 | 39 |
CAN1 | GCLK_CAN1 | 40 |
ETH | GCLK_ETH_TX | 41 |
GCLK_ETH_TSU | 42 | |
SQI | GCLK_SQI | 43 |
SDMMC0 | GLCK_SDMMC0 | 44 |
SDMMC1 | GLCK_SDMMC1 | 45 |
USB | GCLK_USB | 46 |
CPU0 | GCLK_CPU0_TRACE | 47 |