21.7.3 Interrupt Flag Status and Clear

Note: Subsequent to an interrupt flag being cleared, the flag must be read back to verify the clear before exiting the ISR. Failure to do this can result in duplicate interrupts.

Table 21-4. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	INTFLAG
Offset:	0x08
Reset:	0x00000000
Property:	–


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
						XOSC32KFAIL		XOSC32KRDY
Access						R/W/HS/HC		R/W/HS/HC
Reset						0		0

Bit 2 – XOSC32KFAIL XOSC32K Clock Failure Detection

Note: Writing a '0' to this bit has no effect.

This bit is set by hardware under the following conditions:

This flag is set by hardware on a zero-to-one transition of the XOSC32K Clock Failure Detection bit in the (STATUS.XOSC32KFAIL) register and will generate an Interrupt request if INTENSET.XOSC32KFAIL is '1'

This bit is cleared under the following conditions:

Writing a '1' to this bit will clear the XOSC32K Clock Failure Detection flag

Value	Description
0	No XOSC32K 32.768kHz Clock Fail Detected.
1	XOSC32K 32.768kHz Clock Fail Detected.

Bit 0 – XOSC32KRDY XOSC32K Ready

Note: Writing a '0' to this bit has no effect.

This bit is set by hardware under the following conditions:

This flag is set by a zero-to-one transition of the XOSC32K Ready bit in the Status register (STATUS.XOSC32KRDY) and will generate an interrupt request if INTENSET.XOSC32KRDY=1

This bit is cleared under the following conditions:

Writing a '1' to this bit will clear the XOSC32K Ready interrupt flag

Value	Description
0	The XOSC32K Ready interrupt is disabled.
1	The XOSC32K Ready interrupt is enabled.