16.12.6 Testing of On-Board Memories MBIST (Global Memory BIST)
The DSU implements a feature for automatic testing of memory also known as Global Memory Built-In Self Test (Global MBIST). Only memory mapped memories (accessible from the DSU AHB Host) can be tested.
The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect a wide range of memory defects, while still keeping a linear run time.
Algorithm
The MBIST algorithm is provided in the following table:
| Mnemonic(STATUSC.STATE) | Phase | Iteration | Steps |
|---|---|---|---|
| MBIST_FILL | Write all bits to zero (32-bit AHB writes). No MBIST fault is detected in this phase. | For all words (ascending) | LENGTH |
| MBIST_SET1 | 32-bit read at address ADDR. Check that bit INDEX is ‘0’. 32-bit write at address ADDR writes previously read data with bit INDEX ‘1’. | For all words (descending)For all bits (descending) | LENGTH*32 |
| MBIST_SET2 | 32-bit read at address ADDR. Check that bit INDEX is ‘1’. 32-bit write at address ADDR writes previously read data with bit INDEX ‘0’. | SET2, SET2B sequence: For all words (ascending) For all bits (ascending) | 2*LENGTH*32 |
| MBIST_SET2B | 32-bit read at address ADDR. Check that bit INDEX is ‘0’. 32-bit write at address ADDR writes previously read data with bit INDEX ‘1’. | ||
| MBIST_CLEAR1 | 32-bit read at address ADDR. Check that bit INDEX is ‘1’. 32-bit write at address ADDR writes previously read data with bit INDEX ‘0’. | For all words (ascending) For all bits (ascending) | LENGTH*32 |
| MBIST_CLEAR2 | 32-bit read at address ADDR. Check that bit INDEX is ‘0’. 32-bit write at address ADDR writes previously read data with bit INDEX ‘1’. | CLEAR2, CLEAR2B sequence: For all words (ascending) For all bits (ascending) | 2*LENGTH*32 |
| MBIST_CLEAR2B | 32-bit read at address ADDR. Check that bit INDEX is ‘1’. 32-bit write at address ADDR writes previously read data with bit INDEX ‘0’. | ||
| MBIST_READ | 32-bit read Check that all bits read as zero. (INDEX is not relevant in this phase.) | For all words (ascending) (pipelined reads) | LENGTH |
The specific implementation used has a run time that depends on the CPU clock frequency and the number of bytes tested in the RAM. The detected faults are: as follows:
- Address decoder faults
- Stuck-at faults
- Transition faults
- Coupling faults
- Linked Coupling faults
Starting MBIST
To test a memory, write the start address of the memory to the ADDR.ADDR bit field, and the size of the memory into the LENGTH register. When LENGTH = 0 the algorithm ends immediately (STATUS.DONE = 1 without any actual check).
For best test coverage, an entire physical memory block must be tested at once. It is possible to test only a subset of a memory, but the test coverage will then be somewhat lower.
The actual test is started by writing the MBIST command into CTRL.CMD. A running MBIST operation can be canceled by writing a '1' to CTRL.SWRST.
Interpreting the Results
When the operation is completed, STATUSA.DONE is set. STATUSA.BERR indicates whether a bus error occurred, in this case the state machine returns to IDLE state immediately (and sets STATUSA.DONE). STATUSA.FAIL indicates that a fault has been detected. There are three different modes:
| ADDR.AMOD | Description |
|---|---|
| 0x0 | Exit on Error |
| 0x1 | Pause on Error |
| 0x2 | Reserved |
| 0x3 | Reserved |
ADDR.AMOD = 0: exit-on-error (default)
In this mode, the algorithm terminates either when a fault is detected (reported as STATUSA.FAIL) or when a bus error is detected (reported as STATUSA.BERR) or upon successful completion. STATUSA.DONE rises upon completion (with or without errors). STATUSC is copied to the DATA register upon error detection. Users must read the DATA register to locate the fault.
ADDR.AMOD = 1: pause-on-error
In this mode, the MBIST algorithm is paused when an error is detected and STATUSA.FAIL is asserted. Users must ensure STATUSA.FAIL is 0 prior to start the algorithm. Once started and once a fault has been detected the state machine waits for users to clear STATUSA.FAIL by writing a '1' into STATUSA.FAIL to resume the algorithm. Prior to resuming, users can read the STATUSC and ADDR registers to locate the fault. Bus errors stop the MBIST algorithm at any time (STATUSA.DONE and STATUSA.BERR both asserted).
Locating Faults
If the test stops with STATUSA.FAIL high, one or more bits have failed the test. The fault location depends on the selected mode and the state of the state machine when the fault was detected.
All accesses on the bus system are pipelined. In states where a read is followed by a write, the state machine stops after the write is posted on the bus at the same address, therefore the context does not change, error reporting is exact. On the other hand, the MBIST_READ state performs pipelined 32-bit reads. This means that the returned data from the bus is checked while a new read is requested on the bus. Therefore if a fault is detected, it is located on the previous word (at address ADDR-4).
Exit on error mode:
| DATA.STATE | Fault location |
|---|---|
| MBIST FILL | Not Applicable |
| MBIST SET1 | address:
ADDR bit: DATA.INDEX |
| MBIST SET2 | |
| MBIST SET2B | |
| MBIST CLEAR1 | |
| MBIST CLEAR2 | |
| MBIST CLEAR2B | |
| MBIST READ | address: ADDR-4 bit: any of the 32 bits |
| STATUSC.STATE | Fault location |
|---|---|
| MBIST_FILL | Not Applicable |
| MBIST_SET1 | address:
ADDR bit: STATUSC.INDEX |
| MBIST_SET2 | |
| MBIST_SET2B | |
| MBIST_CLEAR1 | |
| MBIST_CLEAR2 | |
| MBIST_CLEAR2B | |
| MBIST_READ | address: ADDR-4 bit: any of the 32 bits |
Fault Injection
This feature supports verifying that any ‘stuck-at’ fault can be caught by the MARCH-LR state machine and therefore is not supposed to be used very often. To minimize the gate-count of this feature, MBFI0 is an alias to the shared register used by DCC0 and BCC0, MBFI1 is an alias to the shared register used by DCC1 and BCC1. Therefore the fault injection mechanism should be used with extreme care if intended to operate along with data and boot communication channels. The MBFI0 and MBFI1 registers are write-protected when CFG.MBFI is 0. As these registers are not asynchronously reset it is recommended to clear them before attempting any MBIST operation with fault injection enabled.
Faults are injected in the data received by the MBIST state machine coming out from the DSU AHB Host when CFG.MBFI is high and when there is an address match between the address configuration held in MBFI0 and MBFI1 and the address presented by the DSU AHB Host.
There is an address match when:
- MBFI0.AMMOD = 1(ALWAYS) (all addresses match in this case)
- When ((DSU AHB Host byte address[31:2]) and ~{6'h00,MBFI0.AMMSK} = MBFI1.ADDR and ~{6'h00,MBFI0.AMMSK})
Each ONE written at position x of AMMSK indicates that the byte address bit x+2 generated by the DSU AHB host during MBIST operation matches (MBFI0.AMMSK and MBFI1.ADDR are word addresses, not Byte addresses).
Only a single fault can be injected at a time. The type of fault is configured by the MBFI0.FTYPE which is either STUCKAT0 (0) or STUCKAT1 (1). MBFI0.BIDX indicates the bit position of the fault.