1 Silicon Issue Summary

Legend

-
Erratum is not applicable.
X
Erratum is applicable.
Peripheral Short Description Valid for Silicon Revision
Rev. A4(1) Rev. A5 Rev. B0
Device 2.2.1 Some Reserved Fuse Bits Are ‘1’ X - -
2.2.2 Increased Current Consumption May Occur When VDD Drops X X -
2.2.3 CRC Check During Reset Initialization Is not Functional X - -
2.2.4 Write Operation Lost if Consecutive Writes to Specific Address Spaces X X X
ADC 2.3.1 Increased Offset in Single-Ended Mode X - -
CCL 2.4.1 The CCL Must be Disabled to Change the Configuration of a Single LUT X X -
2.4.2 The LINK Input Source Selection for LUT3 Is not Functional on 28- and 32-Pin Devices X - -
CLKCTRL 2.5.1 External Clock/Crystal Status Bit is Not Set When the External Clock Source is Ready X - -
2.5.2 RUNSTDBY is Not Functional When Using External Clock Sources X - -
2.5.3 PLL Status not Working as Expected X X -
2.5.4 The PLL Will Not Run when Using XOSCHF with an External Crystal X X -
DAC 2.6.1 DAC Output Buffer Lifetime Drift X X -
NVMCTRL 2.7.1 Flash Multi-Page Erase Can Erase Write Protected Section X X -
2.7.2 NVM_EEPROM_ERASE Command does Not Respect Write Protect X X X
OPAMP 2.8.1 OPAMP Consume More Power Than Expected X - -
2.8.2 The Input Range Select is Read-Only X - -
PORT 2.9.1 PD0 Input Buffer is Floating X X X
RSTCTRL 2.10.1 BOD Registers not Reset When UPDI Is Enabled X - -
SPI 2.11.1 Alternative 2 Pin Position is Non-Functional for SPI1 with 48-Pin Devices X X -
TCA 2.12.1 Restart Will Reset Counter Direction in NORMAL and FRQ Mode X X -
TCB 2.13.1 CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM Mode X X -
TCD 2.14.1 Asynchronous Input Events not Working When TCD Counter Prescaler Is Used X X -
2.14.2 CMPAEN Controls All WOx for Alternative Pin Functions X X -
2.14.3 Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is 0 or Dual Slope Mode is Used X X X
TWI 2.15.1 The Output Pin Override Does not Function as Expected X X -
2.15.2 Flush Non-Functional X X X
USART 2.16.1 Open-Drain Mode Does not Work When TXD Is Configured as Output X X -
2.16.2 Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode X X -
2.16.3 Receiver Non-Functional after Detection of Inconsistent Synchronization Field X X X
ZCD 2.17.1 All ZCD Output Selection Bits Are Tied to the ZCD0 Bit X - -
Note:
  1. This revision is the initial release of the silicon.