Introduction

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The Libero® SoC Design Suite offers high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools for designing with Microchip FPGA and SoC device families. It provides you with an integrated hardware tool suite incorporating RTL entry through bitstream programming, a rich IP library, and complete reference designs and development kits. Libero SoC Design Suite includes SmartHLS™ compiler software for abstracted high-level synthesis development flow, which shortens design time, simplifies verification, and accelerates time to market for designs using our FPGAs.

Use Libero SoC v2025.1 for designing with the following Microchip devices:

RT PolarFire, RT PolarFire SoC and RTG4™ Rad-Tolerant FPGAs
PolarFire® SoC and SmartFusion® 2 SoC FPGAs
PolarFire and IGLOO® 2 FPGAs

To design with older Microchip FPGA family devices, use Libero SoC v11.9 or Libero IDE v9.2 and its subsequent service packs.

To access datasheets, silicon user guides, tutorials, and application notes, visit the Microchip website, navigate to the relevant product family page, and then click the Documentation tab. Development kits and boards are listed in the Kits and Hardware tab.

Important: Libero SoC v2025.1 does not support Classic Constraint flow. IGLOO2, SmartFusion2, and RTG4 projects using the “Classic” flow cannot be opened in this release. A migration path is available for transitioning from the Classic Constraint Flow to the Enhanced Constraint Flow. For more information, see Migrating an Existing Project Created with Classic Constraint Flow to Enhanced Constraint Flow.

Attention: For your reference, Microchip provides a comprehensive library of Libero SoC Design Suite release notes, available here.