4.2.1 Xplained Pro Standard Extension Headers
The ATtiny817 Xplained Pro headers EXT1 and EXT3 offer access to the I/O of the microcontroller to expand the board, e.g., by connecting extensions to the board. These headers are based on the standard extension header specified in the table below. The headers have a pitch of 2.54 mm.
EXT1 Pin | ATtiny817 Pin | Function | Shared Functionality |
---|---|---|---|
1 [ID] | - | - | Communication line to the ID chip on an extension board |
2 [GND] | - | - | Ground |
3 [ADC(+)] | PA6 | AIN6 | QTouch Button 1 |
4 [ADC(-)] | PA7 | AIN7 | QTouch Button 2 |
5 [GPIO1] | PB7 | GPIO | - |
6 [GPIO2] | PB4 | GPIO | LED0 |
7 [PWM(+)] | PB0 | TC/W0 | - |
8 [PWM(-)] | PB1 | TC/W1 | - |
9 [IRQ/GPIO] | PA5 | IRQ/GPIO | - |
10 [SPI_SS_B/GPIO] | PA4 | GPIO | - |
11 [I²C_SDA] | PA1 | I²C SDA | EXT3 and EDBG I²C |
12 [I²C_SCL] | PA2 | I²C SCL | EXT3 and EDBG I²C |
13 [USART_RX] | PB3 | UART RX | EXT3, EDBG CDC, and Crystal (1) |
14 [USART_TX] | PB2 | UART TX | EXT3, EDBG CDC, and Crystal (1) |
15 [SPI_SS_A] | PC3 | SPI SS | - |
16 [SPI_MOSI] | PC2 | SPI MOSI | EXT3 and EDBG SPI |
17 [SPI_MISO] | PC1 | SPI MISO | EXT3 and EDBG SPI |
18 [SPI_SCK] | PC0 | SPI SCK | EXT3 and EDBG SPI |
19 [GND] | - | - | Ground |
20 [VCC] | - | - | Power for extension board |
1) Not connected by default, see Connecting the 32.768 kHz Crystal for more information.
Note: Signal functions in italic use
alternative pin location. These have to be configured in the PORTMUX register of the
device.
EXT3 Pin | ATtiny817 Pin | Function | Shared Functionality |
---|---|---|---|
1 [ID] | - | - | Communication line to the ID chip on an extension board |
2 [GND] | - | - | Ground |
3 [ADC(+)] | - | - | |
4 [ADC(-)] | - | - | |
5 [GPIO1] | PC5 | GPIO | SW1 and UPDI debug connector |
6 [GPIO2] | - | - | |
7 [PWM(+)] | - | - | |
8 [PWM(-)] | - | - | |
9 [IRQ/GPIO] | PB6 | IRQ/GPIO | EDBG DGI |
10 [SPI_SS_B/GPIO] | PB5 | GPIO | SW0 and EDBG DGI |
11 [I²C_SDA] | PA1 | I²C SDA | EXT1 and EDBG I²C |
12 [I²C_SCL] | PA2 | I²C SCL | EXT1 and EDBG I²C |
13 [USART_RX] | PB3 | UART RX | EXT1, EDBG CDC, and Crystal (1) |
14 [USART_TX] | PB2 | UART TX | EXT1, EDBG CDC, and Crystal (1) |
15 [SPI_SS_A] | PA3 | GPIO / SPI_SS | - |
16 [SPI_MOSI] | PC2 | SPI MOSI | EXT1 and EDBG SPI |
17 [SPI_MISO] | PC1 | SPI MISO | EXT1 and EDBG SPI |
18 [SPI_SCK] | PC0 | SPI SCK | EXT1 and EDBG SPI |
19 [GND] | - | - | Ground |
20 [VCC] | - | - | Power for extension board |
1) Not connected by default, see Connecting the 32.768 kHz Crystal for more information.
Note: Signal functions in italic use
alternative pin location. These have to be configured in the PORTMUX register of the
device.