1.1 CVD Operation

The ADC2 module must be configured appropriately to utilize the internal capacitive voltage divider hardware to sense the capacitance on an analog channel. The CVD uses the internal ADC2 sample and hold capacitor (CHOLD) to form a voltage divider with an external conductive sensor. Through a series of steps, this allows the ADC2 to capture the voltage on CHOLD, which is directly related to the capacitance of the sensor tied to the channel. The internal ADC2 sample and hold capacitance value may vary between devices, so it is important to refer to the device data sheet to verify specific electrical specifications. Figure 1-2 shows the waveform for a differential CVD measurement.

CVD operation begins with CHOLD being disconnected from the path that connects it to the capacitive sensor. Doing this allows each capacitive component to be precharged to a known voltage level (VDD or VSS). When the precharge stage is complete, the acquisition stage of the CVD operation can begin. At this time, the path that connects CHOLD to the external sensor is reconnected, allowing the voltage level between the two capacitive components to equally distribute. When CHOLD and the external conductive sensor are connected, a capacitive voltage divider is created. The ADC2 can then be used to measure the voltage level of CHOLD and determine the capacitance of the channel.

Figure 1-1. Hardware Capacitive Voltage Divider Block Diagram
Figure 1-2. Differential CVD Measurement Waveform

The CVD feature allows users to quickly configure the ADC2 module to be used for capacitive sensing applications in software. The registers associated with the configuration of the CVD are listed below.

  • ADC Precharge Polarity (ADCON1)
  • 13-Bit ADC Precharge Time (ADPREL/H)
  • ADC Acquisition Time (ADACQL/H)
  • Additional Sample and Hold Capacitor configuration (ADCAP)
  • Guard Ring Outputs and Polarity (ADCON1)