20.3.1 DDR Configuration Register

Name: SFR_DDRCFG
Offset: 0x04
Reset: 0x00000001
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       FDQSIENFDQIEN 
Access R/WR/W 
Reset 00 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
          
Access  
Reset  

Bit 17 – FDQSIEN Force DDR_DQS Input Buffer Always On

FDQSIEN = 1 is used to force the selection of the analog comparator inside the IO. If this bit is cleared, the DDR controller automatically manages the selection of the analog comparator. Forcing the bit to 0 reduces power consumption.
ValueDescription
0 DDR_DQS input buffer controlled by DDR controller.
1 DDR_DQS input buffer always on.

Bit 16 – FDQIEN Force DDR_DQ Input Buffer Always On

FDQIEN = 1 is used to force the selection of the analog comparator inside the IO. If this bit is cleared, the DDR controller automatically manages the selection of the analog comparator. Forcing the bit to 0 reduces power consumption.
ValueDescription
0 DDR_DQ input buffer controlled by DDR controller.
1 DDR_DQ input buffer always on.