30.6.3.1 PTC Digital Controller Operations

  • Sensing mode (mutual or self)
  • Control of the ADC 10-bit SAR state machine single ADC conversion or free run mode (comparator and ADC data/accumulator register)
  • Digital gain up to 32 and averaging up to 64 ADC codes
  • Selection of the filtering resistance (0, 20, 50 or 100 kΩ)
  • Adjustment of the compensation capacitor up to 30 pF
  • Adjustment of the integration capacitor up to 30 pF
  • Frequency hopping(1) implementation (modification of the sampling rate to avoid synchronous parasitic noise)
  • Channel Change Delay Selection CDS(2) (settling time)
  • Prescaling (1, 1/2, 1/4, 1/8), 4 MHz down to ADC_CLK
Note:
  1. A programmable sampling delay can be used to choose (modify) the sampling frequency that is best suited in an application where other periodic noise sources may otherwise disturb the sampling. Frequency hopping can also be modified automatically from one sampling cycle to another, by setting the software driver parameters.
  2. CDS bits define the delay when changing input channels. The delay allows the analog circuits to settle on a new (Y) channel or channel pair (X-Y). The delay is application-dependent, and therefore this option enables the user to select a suitable delay. The delay is expressed as a number of PTC clock cycles.