49.8.8 SPI Status Register
| Name: | SPI_SR |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RXFPTEF | TXFPTEF | RXFTHF | RXFFF | RXFEF | TXFTHF | TXFFF | TXFEF | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SPIENS | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMP | UNDES | TXEMPTY | NSSR | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVRES | MODF | TDRE | RDRF | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 31 – RXFPTEF Receive FIFO Pointer Error Flag
See FIFO Pointer Error for details.
| Value | Description |
|---|---|
| 0 | No Receive FIFO pointer occurred. |
| 1 | Receive FIFO pointer error occurred. Receiver must be reset. |
Bit 30 – TXFPTEF Transmit FIFO Pointer Error Flag
See FIFO Pointer Error for details.
| Value | Description |
|---|---|
| 0 | No Transmit FIFO pointer occurred. |
| 1 | Transmit FIFO pointer error occurred. Transceiver must be reset. |
Bit 29 – RXFTHF Receive FIFO Threshold Flag
| Value | Description |
|---|---|
| 0 | Number of unread data in Receive FIFO is below RXFTHRES threshold or RXFTH flag has been cleared. |
| 1 | Number of unread data in Receive FIFO has reached RXFTHRES threshold (coming from “below threshold” state to “equal or above threshold” state). |
Bit 28 – RXFFF Receive FIFO Full Flag
| Value | Description |
|---|---|
| 0 | Receive FIFO is not empty or RXFE flag has been cleared. |
| 1 | Receive FIFO has become full (coming from “not full” state to “full” state). |
Bit 27 – RXFEF Receive FIFO Empty Flag
| Value | Description |
|---|---|
| 0 | Receive FIFO is not empty or RXFE flag has been cleared. |
| 1 | Receive FIFO has become empty (coming from “not empty” state to “empty” state). |
Bit 26 – TXFTHF Transmit FIFO Threshold Flag (cleared on read)
| Value | Description |
|---|---|
| 0 | Number of data in Transmit FIFO is above TXFTHRES threshold. |
| 1 | Number of data in Transmit FIFO has reached TXFTHRES threshold since the last read of SPI_SR. |
Bit 25 – TXFFF Transmit FIFO Full Flag (cleared on read)
| Value | Description |
|---|---|
| 0 | Transmit FIFO is not full or TXFF flag has been cleared. |
| 1 | Transmit FIFO has been filled since the last read of SPI_SR. |
Bit 24 – TXFEF Transmit FIFO Empty Flag (cleared on read)
| Value | Description |
|---|---|
| 0 | Transmit FIFO is not empty. |
| 1 | Transmit FIFO has been emptied since the last read of SPI_SR. |
Bit 16 – SPIENS SPI Enable Status
| Value | Description |
|---|---|
| 0 | SPI is disabled. |
| 1 | SPI is enabled. |
Bit 11 – CMP Comparison Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No received character matched the comparison criteria programmed in VAL1 and VAL2 fields in SPI_CMPR since the last read of SPI_SR. |
| 1 | A received character matched the comparison criteria since the last read of SPI_SR. |
Bit 10 – UNDES Underrun Error Status (Client mode only) (cleared on read)
| Value | Description |
|---|---|
| 0 | No underrun has been detected since the last read of SPI_SR. |
| 1 | A transfer starts whereas no data has been loaded in SPI_TDR. |
Bit 9 – TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR)
| Value | Description |
|---|---|
| 0 | As soon as data is written in SPI_TDR. |
| 1 | SPI_TDR and internal shift register are empty. If a transfer delay has been defined, TXEMPTY is set after the end of this delay. |
Bit 8 – NSSR NSS Rising (cleared on read)
| Value | Description |
|---|---|
| 0 | No rising edge detected on NSS pin since the last read of SPI_SR. |
| 1 | A rising edge occurred on NSS pin since the last read of SPI_SR. |
Bit 3 – OVRES Overrun Error Status (cleared on read)
An overrun occurs when SPI_RDR is loaded at least twice from the internal shift register since the last read of SPI_RDR.
| Value | Description |
|---|---|
| 0 | No overrun has been detected since the last read of SPI_SR. |
| 1 | An overrun has occurred since the last read of SPI_SR. |
Bit 2 – MODF Mode Fault Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No mode fault has been detected since the last read of SPI_SR. |
| 1 | A mode fault occurred since the last read of SPI_SR. |
Bit 1 – TDRE Transmit Data Register Empty (cleared by writing SPI_TDR)
When FIFOs are disabled:
0: Data has been written to SPI_TDR and not yet transferred to the internal shift register.
1: The last data written in SPI_TDR has been transferred to the internal shift register.
TDRE is cleared when the SPI is disabled or at reset. Enabling the SPI sets the TDRE flag.
When FIFOs are enabled:
0: Transmit FIFO is full and cannot accept more data.
1: Transmit FIFO is not full; one or more data can be written according to TXRDYM field configuration.
TDRE behavior with FIFOs enabled is illustrated in section TXEMPTY, TDRE and RDRF Behavior.
Bit 0 – RDRF Receive Data Register Full (cleared by reading SPI_RDR)
When FIFOs are disabled:
0: No data has been received since the last read of SPI_RDR.
1: Data has been received and the received data has been transferred from the internal shift register to SPI_RDR since the last read of SPI_RDR.
When FIFOs are enabled:
0: Receive FIFO is empty; no data to read.
1: At least one unread data is in the Receive FIFO.
RDRF behavior with FIFOs enabled is illustrated in section TXEMPTY, TDRE and RDRF Behavior.