7 Pinout

I/Os for each peripheral are grouped into IO sets, listed in the column ‘IO Set’ in the pinout table below. For all peripherals, it is mandatory to use I/Os that belong to the same IO set. The timings are not guaranteed when IOs from different IO sets are mixed.
Table 7-1. Pin Description
289-pin BGAPower RailI/O TypePrimaryAlternatePIO PeripheralReset State

(Signal, Dir, PU, PD, HiZ, ST)(1)(2)

SignalDirSignalDirFuncSignalDirIO
Set
U11VDDSDMMCGPIO_EMMCPA0I/OASDMMC0_CKI/O1PIO, I, PU, ST
BQSPI0_SCKO1
FD0I/O2
P10VDDSDMMCGPIO_EMMCPA1I/OASDMMC0_CMDI/O1PIO, I, PU, ST
BQSPI0_CSO1
FD1I/O2
T11VDDSDMMCGPIO_EMMCPA2I/OASDMMC0_DAT0I/O1PIO, I, PU, ST
BQSPI0_IO0I/O1
FD2I/O2
R10VDDSDMMCGPIO_EMMCPA3I/OASDMMC0_DAT1I/O1PIO, I, PU, ST
BQSPI0_IO1I/O1
FD3I/O2
U12VDDSDMMCGPIO_EMMCPA4I/OASDMMC0_DAT2I/O1PIO, I, PU, ST
BQSPI0_IO2I/O1
FD4I/O2
T12VDDSDMMCGPIO_EMMCPA5I/OASDMMC0_DAT3I/O1PIO, I, PU, ST
BQSPI0_IO3I/O1
FD5I/O2
R12VDDSDMMCGPIO_EMMCPA6I/OASDMMC0_DAT4I/O1PIO, I, PU, ST
BQSPI1_SCKO1
DTIOA5I/O1
EFLEXCOM2_IO0I/O1
FD6I/O2
T13VDDSDMMCGPIO_EMMCPA7I/OASDMMC0_DAT5I/O1PIO, I, PU, ST
BQSPI1_IO0I/O1
DTIOB5I/O1
EFLEXCOM2_IO1I/O1
FD7I/O2
N10VDDSDMMCGPIO_EMMCPA8I/OASDMMC0_DAT6I/O1PIO, I, PU, ST
BQSPI1_IO1I/O1
DTCLK5I1
EFLEXCOM2_IO2I/O1
FNWE/NANDWEO2
N11VDDSDMMCGPIO_EMMCPA9I/OASDMMC0_DAT7I/O1PIO, I, PU, ST
BQSPI1_IO2I/O1
DTIOA4I/O1
EFLEXCOM2_IO3O1
FNCS3O2
U13VDDSDMMCGPIO_EMMCPA10I/OASDMMC0_RSTNO1PIO, I, PU, ST
BQSPI1_IO3I/O1
DTIOB4I/O1
EFLEXCOM2_IO4O1
FA21/NANDALEO2
P15VDDIOP1GPIOPA11I/OASDMMC0_1V8SELO1PIO, I, PU, ST
BQSPI1_CSO1
DTCLK4I1
FA22/NANDCLEO2
N15VDDIOP1GPIOPA12I/OASDMMC0_WPI1PIO, I, PU, ST
BIRQI1
FNRD/NANDOEO2
P16VDDIOP1GPIOPA13I/OASDMMC0_CDI1PIO, I, PU, ST
EFLEXCOM3_IO1I/O1
FD8I/O2
M14VDDIOP1GPIO_QSPIPA14I/OASPI0_SPCKI/O1PIO, I, PU, ST
BTK1I/O1
CQSPI0_SCKO2
DI2SC1_MCKO2
EFLEXCOM3_IO2I/O1
FD9I/O2
N16VDDIOP1GPIOPA15I/OASPI0_MOSII/O1PIO, I, PU, ST
BTF1I/O1
CQSPI0_CSO2
DI2SC1_CKI/O2
EFLEXCOM3_IO0I/O1
FD10I/O2
M10VDDIOP1GPIO_IOPA16I/OASPI0_MISOI/O1PIO, I, PU, ST
BTD1O1
CQSPI0_IO0I/O2
DI2SC1_WSI/O2
EFLEXCOM3_IO3I/O1
FD11I/O2
N17VDDIOP1GPIO_IOPA17I/OASPI0_NPCS0I/O1PIO, I, PU, ST
BRD1I1
CQSPI0_IO1I/O2
DI2SC1_DI0I2
EFLEXCOM3_IO4O1
FD12I/O2
U14VDDIOP1GPIO_IOPA18I/OASPI0_NPCS1O1PIO, I, PU, ST
BRK1I/O1
CQSPI0_IO2I/O2
DI2SC1_DO0O2
ESDMMC1_DAT0I/O1
FD13I/O2
T14VDDIOP1GPIO_IOPA19I/OASPI0_NPCS2O1PIO, I, PU, ST
BRF1I/O1
CQSPI0_IO3I/O2
DTIOA0I/O1
ESDMMC1_DAT1I/O1
FD14I/O2
P12VDDIOP1GPIO_IOPA20I/OASPI0_NPCS3O1PIO, I, PU, ST
DTIOB0I/O1
ESDMMC1_DAT2I/O1
FD15I/O2
R13VDDIOP1GPIO_IOPA21I/OAIRQI2PIO, I, PU, ST
BPCK2O3
DTCLK0I1
ESDMMC1_DAT3I/O1
FNANDRDYI2
U15VDDIOP1GPIO_QSPIPA22I/OAFLEXCOM1_IO2I/O1PIO, I, PU, ST
BD0I/O1
CTCKI4
DSPI1_SPCKI/O2
ESDMMC1_CKI/O1
FQSPI0_SCKO3
U16VDDIOP1GPIOPA23I/OAFLEXCOM1_IO1I/O1PIO, I, PU, ST
BD1I/O1
CTDII4
DSPI1_MOSII/O2
FQSPI0_CSO3
T15VDDIOP1GPIO_IOPA24I/OAFLEXCOM1_IO0I/O1PIO, I, PU, ST
BD2I/O1
CTDOO4
DSPI1_MISOI/O2
FQSPI0_IO0I/O3
U17VDDIOP1GPIO_IOPA25I/OAFLEXCOM1_IO3O1PIO, I, PU, ST
BD3I/O1
CTMSI4
DSPI1_NPCS0I/O2
FQSPI0_IO1I/O3
P13VDDIOP1GPIO_IOPA26I/OAFLEXCOM1_IO4O1PIO, I, PU, ST
BD4I/O1
CNTRSTI4
DSPI1_NPCS1O2
FQSPI0_IO2I/O3
T16VDDIOP1GPIO_IOPA27I/OATIOA1I/O2PIO, I, PU, ST
BD5I/O1
CSPI0_NPCS2O2
DSPI1_NPCS2O2
ESDMMC1_RSTNO1
FQSPI0_IO3I/O3
R16VDDIOP1GPIOPA28I/OATIOB1I/O2PIO, I, PU, ST
BD6I/O1
CSPI0_NPCS3O2
DSPI1_NPCS3O2
ESDMMC1_CMDI/O1
FCLASSD_L0O1
T17VDDIOP1GPIOPA29I/OATCLK1I2PIO, I, PU, ST
BD7I/O1
CSPI0_NPCS1O2
ESDMMC1_WPI1
FCLASSD_L1O1
R15VDDIOP1GPIOPA30I/OBNWE/NANDWEO1PIO, I, PU, ST
CSPI0_NPCS0I/O2
DPWMH0O1
ESDMMC1_CDI1
FCLASSD_L2O1
R17VDDIOP1GPIOPA31I/OBNCS3O1PIO, I, PU, ST
CSPI0_MISOI/O2
DPWML0O1
FCLASSD_L3O1
J8VDDIOP0GPIOPB0I/OBA21/NANDALEO1PIO, I, PU, ST
CSPI0_MOSII/O2
DPWMH1O1
A8VDDIOP0GPIOPB1I/OBA22/NANDCLEO1PIO, I, PU, ST
CSPI0_SPCKI/O2
DPWML1O1
FCLASSD_R0O1
A7VDDIOP0GPIOPB2I/OBNRD/NANDOEO1PIO, I, PU, ST
DPWMFI0I1
FCLASSD_R1O1
A6VDDIOP0GPIOPB3I/OAURXD4I1PIO, I, PU, ST
BD8I/O1
CIRQI3
DPWMEXTRG1I1
FCLASSD_R2O1
B6VDDIOP0GPIOPB4I/OAUTXD4O1PIO, I, PU, ST
BD9I/O1
CFIQI4
FCLASSD_R3O1
B7VDDIOP0GPIO_QSPIPB5I/OATCLK2I1PIO, I, PU, ST
BD10I/O1
CPWMH2O1
DQSPI1_SCKO2
FGTSUCOMPO3
C7VDDIOP0GPIOPB6I/OATIOA2I/O1PIO, I, PU, ST
BD11I/O1
CPWML2O1
DQSPI1_CSO2
FGTXERO3
C6VDDIOP0GPIO_IOPB7I/OATIOB2I/O1PIO, I, PU, ST
BD12I/O1
CPWMH3O1
DQSPI1_IO0I/O2
FGRXCKI3
A5VDDIOP0GPIO_IOPB8I/OATCLK3I1PIO, I, PU, ST
BD13I/O1
CPWML3O1
DQSPI1_IO1I/O2
FGCRSI3
A4VDDIOP0GPIO_IOPB9I/OATIOA3I/O1PIO, I, PU, ST
BD14I/O1
CPWMFI1I1
DQSPI1_IO2I/O2
FGCOLI3
H8VDDIOP0GPIO_IOPB10I/OATIOB3I/O1PIO, I, PU, ST
BD15I/O1
CPWMEXTRG2I1
DQSPI1_IO3I/O2
FGRX2I3
B5VDDIOP0GPIOPB11I/OALCDDAT0O1PIO, I, PU, ST
BA0/NBS0O1
CURXD3I3
DPDMIC_DAT2
FGRX3I3
D6VDDIOP0GPIOPB12I/OALCDDAT1O1PIO, I, PU, ST
BA1O1
CUTXD3O3
DPDMIC_CLK2
FGTX2O3
B4VDDIOP0GPIOPB13I/OALCDDAT2O1PIO, I, PU, ST
BA2O1
CPCK1O3
FGTX3O3
C5VDDIOP0GPIO_QSPIPB14I/OALCDDAT3O1PIO, I, PU, ST
BA3O1
CTK1I/O2
DI2SC1_MCKO1
EQSPI1_SCKO3
FGTXCKI/O3
H7VDDIOP0GPIOPB15I/OALCDDAT4O1PIO, I, PU, ST
BA4O1
CTF1I/O2
DI2SC1_CKI/O1
EQSPI1_CSO3
FGTXENO3
D5VDDIOP0GPIO_IOPB16I/OALCDDAT5O1PIO, I, PU, ST
BA5O1
CTD1O2
DI2SC1_WSI/O1
EQSPI1_IO0I/O3
FGRXDVI3
C4VDDIOP0GPIO_IOPB17I/OALCDDAT6O1PIO, I, PU, ST
BA6O1
CRD1I2
DI2SC1_DI0I1
EQSPI1_IO1I/O3
FGRXERI3
A3VDDIOP0GPIO_IOPB18I/OALCDDAT7O1PIO, I, PU, ST
BA7O1
CRK1I/O2
DI2SC1_DO0O1
EQSPI1_IO2I/O3
FGRX0I3
D4VDDIOP0GPIO_IOPB19I/OALCDDAT8O1PIO, I, PU, ST
BA8O1
CRF1I/O2
DTIOA3I/O2
EQSPI1_IO3I/O3
FGRX1I3
B3VDDIOP0GPIOPB20I/OALCDDAT9O1PIO, I, PU, ST
BA9O1
CTK0I/O1
DTIOB3I/O2
EPCK1O4
FGTX0O3
A2VDDIOP0GPIOPB21I/OALCDDAT10O1PIO, I, PU, ST
BA10O1
CTF0I/O1
DTCLK3I2
EFLEXCOM3_IO2I/O3
FGTX1O3
C3VDDIOP0GPIOPB22I/OALCDDAT11O1PIO, I, PU, ST
BA11O1
CTD0O1
DTIOA2I/O2
EFLEXCOM3_IO1I/O3
FGMDCO3
A1VDDIOP0GPIOPB23I/OALCDDAT12O1PIO, I, PU, ST
BA12O1
CRD0I1
DTIOB2I/O2
EFLEXCOM3_IO0I/O3
FGMDIOI/O3
E5VDDIOP0GPIOPB24I/OALCDDAT13O1PIO, I, PU, ST
BA13O1
CRK0I/O1
DTCLK2I2
EFLEXCOM3_IO3I/O3
FISC_D10I3
B2VDDIOP0GPIOPB25I/OALCDDAT14O1PIO, I, PU, ST
BA14O1
CRF0I/O1
EFLEXCOM3_IO4O3
FISC_D11I3
E4VDDIOP0GPIOPB26I/OALCDDAT15O1PIO, I, PU, ST
BA15O1
CURXD0I1
DPDMIC_DAT1
FISC_D0I3
B1VDDIOP0GPIOPB27I/OALCDDAT16O1PIO, I, PU, ST
BA16O1
CUTXD0O1
DPDMIC_CLK1
FISC_D1I3
C2VDDIOP0GPIOPB28I/OALCDDAT17O1PIO, I, PU, ST
BA17O1
CFLEXCOM0_IO0I/O1
DTIOA5I/O2
FISC_D2I3
D3VDDIOP0GPIOPB29I/OALCDDAT18O1PIO, I, PU, ST
BA18O1
CFLEXCOM0_IO1I/O1
DTIOB5I/O2
FISC_D3I3
D2VDDIOP0GPIOPB30I/OALCDDAT19O1PIO, I, PU, ST
BA19O1
CFLEXCOM0_IO2I/O1
DTCLK5I2
FISC_D4I3
C1VDDIOP0GPIOPB31I/OALCDDAT20O1PIO, I, PU, ST
BA20O1
CFLEXCOM0_IO3O1
DTWD0I/O1
FISC_D5I3
P17VDDIOP1GPIOPC0I/OALCDDAT21O1PIO, I, PU, ST
BA23O1
CFLEXCOM0_IO4O1
DTWCK0I/O1
FISC_D6I3
N12VDDIOP1GPIOPC1I/OALCDDAT22O1PIO, I, PU, ST
BA24O1
CCANTX0O1
DSPI1_SPCKI/O1
EI2SC0_CKI/O1
FISC_D7I3
N14VDDIOP1GPIOPC2I/OALCDDAT23O1PIO, I, PU, ST
BA25O1
CCANRX0I1
DSPI1_MOSII/O1
EI2SC0_MCKO1
FISC_D8I3
M15VDDIOP1GPIOPC3I/OALCDPWMO1PIO, I, PU, ST
BNWAITI1
CTIOA1I/O1
DSPI1_MISOI/O1
EI2SC0_WSI/O1
FISC_D9I3
M11VDDIOP1GPIOPC4I/OALCDDISPO1PIO, I, PU, ST
BNWR1/NBS1O1
CTIOB1I/O1
DSPI1_NPCS0I/O1
EI2SC0_DI0I1
FISC_PCKI3
L10VDDIOP1GPIOPC5I/OALCDVSYNCO1PIO, I, PU, ST
BNCS0O1
CTCLK1I1
DSPI1_NPCS1O1
EI2SC0_DO0O1
FISC_VSYNCI3
K10VDDIOP1GPIOPC6I/OALCDHSYNCO1PIO, I, PU, ST
BNCS1O1
CTWD1I/O1
DSPI1_NPCS2O1
FISC_HSYNCI3
M16VDDIOP1GPIO_CLKPC7I/OALCDPCKO1PIO, I, PU, ST
BNCS2O1
CTWCK1I/O1
DSPI1_NPCS3O1
EURXD1I2
FISC_MCKO3
J10VDDIOP1GPIOPC8I/OALCDDENO1PIO, I, PU, ST
BNANDRDYI1
CFIQI1
DPCK0O3
EUTXD1O2
FISC_FIELDI3
D1VDDISCGPIOPC9I/OAFIQI3PIO, I, PU, ST
BGTSUCOMPO1
CISC_D0I1
DTIOA4I/O2
E3VDDISCGPIOPC10I/OALCDDAT2O2PIO, I, PU, ST
BGTXCKI/O1
CISC_D1I1
DTIOB4I/O2
ECANTX0O2
E2VDDISCGPIOPC11I/OALCDDAT3O2PIO, I, PU, ST
BGTXENO1
CISC_D2I1
DTCLK4I2
ECANRX0I2
FA0/NBS0O2
E1VDDISCGPIOPC12I/OALCDDAT4O2PIO, I, PU, ST
BGRXDVI1
CISC_D3I1
DURXD3I1
ETK0I/O2
FA1O2
F3VDDISCGPIOPC13I/OALCDDAT5O2PIO, I, PU, ST
BGRXERI1
CISC_D4I1
DUTXD3O1
ETF0I/O2
FA2O2
F5VDDISCGPIOPC14I/OALCDDAT6O2PIO, I, PU, ST
BGRX0I1
CISC_D5I1
ETD0O2
FA3O2
F2VDDISCGPIOPC15I/OALCDDAT7O2PIO, I, PU, ST
BGRX1I1
CISC_D6I1
ERD0I2
FA4O2
G6VDDISCGPIOPC16I/OALCDDAT10O2PIO, I, PU, ST
BGTX0O1
CISC_D7I1
ERK0I/O2
FA5O2
F1VDDISCGPIOPC17I/OALCDDAT11O2PIO, I, PU, ST
BGTX1O1
CISC_D8I1
ERF0I/O2
FA6O2
H6VDDISCGPIOPC18I/OALCDDAT12O2PIO, I, PU, ST
BGMDCO1
CISC_D9I1
EFLEXCOM3_IO2I/O2
FA7O2
G2VDDISCGPIOPC19I/OALCDDAT13O2PIO, I, PU, ST
BGMDIOI/O1
CISC_D10I1
EFLEXCOM3_IO1I/O2
FA8O2
G3VDDISCGPIOPC20I/OALCDDAT14O2PIO, I, PU, ST
BGRXCKI1
CISC_D11I1
EFLEXCOM3_IO0I/O2
FA9O2
G1VDDISCGPIOPC21I/OALCDDAT15O2PIO, I, PU, ST
BGTXERO1
CISC_PCKI1
EFLEXCOM3_IO3I/O2
FA10O2
H2VDDISCGPIOPC22I/OALCDDAT18O2PIO, I, PU, ST
BGCRSI1
CISC_VSYNCI1
EFLEXCOM3_IO4O2
FA11O2
G5VDDISCGPIOPC23I/OALCDDAT19O2PIO, I, PU, ST
BGCOLI1
CISC_HSYNCI1
FA12O2
H1VDDISCGPIO_CLKPC24I/OALCDDAT20O2PIO, I, PU, ST
BGRX2I1
CISC_MCKO1
FA13O2
H5VDDISCGPIOPC25I/OALCDDAT21O2PIO, I, PU, ST
BGRX3I1
CISC_FIELDI1
FA14O2
J9VDDIOP2GPIOPC26I/OALCDDAT22O2PIO, I, PU, ST
BGTX2O1
DCANTX1O1
FA15O2
H9VDDIOP2GPIOPC27I/OALCDDAT23O2PIO, I, PU, ST
BGTX3O1
CPCK1O2
DCANRX1I1
ETWD0I/O2
FA16O2
E8VDDIOP2GPIOPC28I/OALCDPWMO2PIO, I, PU, ST
BFLEXCOM4_IO0I/O1
CPCK2O1
ETWCK0I/O2
FA17O2
G8VDDIOP2GPIOPC29I/OALCDDISPO2PIO, I, PU, ST
BFLEXCOM4_IO1I/O1
FA18O2
F8VDDIOP2GPIOPC30I/OALCDVSYNCO2PIO, I, PU, ST
BFLEXCOM4_IO2I/O1
FA19O2
D8VDDIOP2GPIOPC31I/OALCDHSYNCO2PIO, I, PU, ST
BFLEXCOM4_IO3O1
CURXD3I2
FA20O2
G10VDDIOP2GPIO_CLKPD0I/OALCDPCKO2PIO, I, PU, ST
BFLEXCOM4_IO4O1
CUTXD3O2
DGTSUCOMPO2
FA23O2
E10VDDIOP2GPIOPD1I/OALCDDENO2PIO, I, PU, ST
DGRXCKI2
FA24O2
G9VDDIOP2GPIO_CLKPD2I/OAURXD1I1PIO, I, PU, ST
DGTXERO2
EISC_MCKO2
FA25O2
K1VDDANAGPIO_ADPD3I/OPTC_X0AUTXD1O1PIO, I, PU, ST
BFIQI2
DGCRSI2
EISC_D11I2
FNWAITI2
J6VDDANAGPIO_ADPD4I/OPTC_X1ATWD1I/O2PIO, I, PU, ST
BURXD2I1
DGCOLI2
EISC_D10I2
FNCS0O2
J4VDDANAGPIO_ADPD5I/OPTC_X2ATWCK1I/O2PIO, I, PU, ST
BUTXD2O1
DGRX2I2
EISC_D9I2
FNCS1O2
J2VDDANAGPIO_ADPD6I/OPTC_X3ATCKI2PIO, I, PU, ST
BPCK1O1
DGRX3I2
EISC_D8I2
FNCS2O2
J7VDDANAGPIO_ADPD7I/OPTC_X4ATDII2PIO, I, PU, ST
CUTMI_RXVALO1
DGTX2O2
EISC_D0I2
FNWR1/NBS1O2
J1VDDANAGPIO_ADPD8I/OPTC_X5ATDOO2PIO, I, PU, ST
CUTMI_RXERRO1
DGTX3O2
EISC_D1I2
FNANDRDYI2
K9VDDANAGPIO_ADPD9I/OPTC_X6ATMSI2PIO, I, PU, ST
CUTMI_RXACTO1
DGTXCKI/O2
EISC_D2I2
J3VDDANAGPIO_ADPD10I/OPTC_X7ANTRSTI2PIO, I, PU, ST
CUTMI_HDISO1
DGTXENO2
EISC_D3I2
M1VDDANAGPIO_ADPD11I/OPTC_Y0ATIOA1I/O3PIO, I, PU, ST
BPCK2O2
CUTMI_LS0O1
DGRXDVI2
EISC_D4I2
FISC_MCKO4
K8VDDANAGPIO_ADPD12I/OPTC_Y1ATIOB1I/O3PIO, I, PU, ST
BFLEXCOM4_IO0I/O2
CUTMI_LS1O1
DGRXERI2
EISC_D5I2
FISC_D4I4
L2VDDANAGPIO_ADPD13I/OPTC_Y2ATCLK1I3PIO, I, PU, ST
BFLEXCOM4_IO1I/O2
CUTMI_CDRCPSEL0I1
DGRX0I2
EISC_D6I2
FISC_D5I4
K4VDDANAGPIO_ADPD14I/OPTC_Y3ATCK(4)I1A, PU, ST
BFLEXCOM4_IO2I/O2
CUTMI_CDRCPSEL1I1
DGRX1I2
EISC_D7I2
FISC_D6I4
K7VDDANAGPIO_ADPD15I/OPTC_Y4ATDI(4)I1PIO, I, PU, ST
BFLEXCOM4_IO3O2
CUTMI_CDRCPDIVENI1
DGTX0O2
EISC_PCKI2
FISC_D7I4
L1VDDANAGPIO_ADPD16I/OPTC_Y5ATDO(4)O1PIO, I, PU, ST
BFLEXCOM4_IO4O2
CUTMI_CDRBISTENI1
DGTX1O2
EISC_VSYNCI2
FISC_D8I4
K2VDDANAGPIO_ADPD17I/OPTC_Y6ATMS(4)I1A, PU, ST
CUTMI_CDRCPSELDIVO1
DGMDCO2
EISC_HSYNCI2
FISC_D9I4
J5VDDANAGPIO_ADPD18I/OPTC_Y7ANTRST(4)I1PIO, I, PU, ST
DGMDIOI/O2
EISC_FIELDI2
FISC_D10I4
K6VDDANAGPIO_ADPD19I/OAD0APCK0O1PIO, I, PU, ST
BTWD1I/O3
CURXD2I3
EI2SC0_CKI/O2
FISC_D11I4
M2VDDANAGPIO_ADPD20I/OAD1ATIOA2I/O3PIO, I, PU, ST
BTWCK1I/O3
CUTXD2O3
EI2SC0_MCKO2
FISC_PCKI4
N1VDDANAGPIO_ADPD21I/OAD2ATIOB2I/O3PIO, I, PU, ST
BTWD0I/O4
CFLEXCOM4_IO0I/O3
EI2SC0_WSI/O2
FISC_VSYNCI4
L4VDDANAGPIO_ADPD22I/OAD3ATCLK2I3PIO, I, PU, ST
BTWCK0I/O4
CFLEXCOM4_IO1I/O3
EI2SC0_DI0I2
FISC_HSYNCI4
M3VDDANAGPIO_ADPD23I/OAD4AURXD2I2PIO, I, PU, ST
CFLEXCOM4_IO2I/O3
EI2SC0_DO0O2
FISC_FIELDI4
L7VDDANAGPIO_ADPD24I/OAD5AUTXD2O2PIO, I, PU, ST
CFLEXCOM4_IO3O3
L6VDDANAGPIO_ADPD25I/OAD6ASPI1_SPCKI/O3PIO, I, PU, ST
CFLEXCOM4_IO4O3
N2VDDANAGPIO_ADPD26I/OAD7ASPI1_MOSII/O3PIO, I, PU, ST
CFLEXCOM2_IO0I/O2
L8VDDANAGPIO_ADPD27I/OAD8ASPI1_MISOI/O3PIO, I, PU, ST
BTCKI3
CFLEXCOM2_IO1I/O2
M4VDDANAGPIO_ADPD28I/OAD9ASPI1_NPCS0I/O3PIO, I, PU, ST
BTDII3
CFLEXCOM2_IO2I/O2
N3VDDANAGPIO_ADPD29I/OAD10ASPI1_NPCS1O3PIO, I, PU, ST
BTDOO3
CFLEXCOM2_IO3O2
DTIOA3I/O3
ETWD0I/O3
L9VDDANAGPIO_ADPD30I/OAD11ASPI1_NPCS2O3PIO, I, PU, ST
BTMSI3
CFLEXCOM2_IO4O2
DTIOB3I/O3
ETWCK0I/O3
M7VDDANAGPIOPD31I/OAADTRGI1PIO, I, PU, ST
BNTRSTI3
CIRQI4
DTCLK3I3
EPCK0O2
L5VDDANApowerVDDANAI
K5GNDANAgroundGNDANAI
M6VDDANAADVREFI
K3VDDANApowerVDDANAI
L3GNDANAgroundGNDANAI
H16,
D16VDDIODDRDDRDDR_VREFI
B12VDDIODDRDDRDDR_D0I/O
A12VDDIODDRDDRDDR_D1I/O
C12VDDIODDRDDRDDR_D2I/O
A13VDDIODDRDDRDDR_D3I/O
A14VDDIODDRDDRDDR_D4I/O
C13VDDIODDRDDRDDR_D5I/O
A15VDDIODDRDDRDDR_D6I/O
B15VDDIODDRDDRDDR_D7I/O
G17VDDIODDRDDRDDR_D8I/O
G16VDDIODDRDDRDDR_D9I/O
H17VDDIODDRDDRDDR_D10I/O
K17VDDIODDRDDRDDR_D11I/O
K16VDDIODDRDDRDDR_D12I/O
J13VDDIODDRDDRDDR_D13I/O
K14VDDIODDRDDRDDR_D14I/O
K15VDDIODDRDDRDDR_D15I/O
B8VDDIODDRDDRDDR_D16I/O
B9VDDIODDRDDRDDR_D17I/O
C9VDDIODDRDDRDDR_D18I/O
A9VDDIODDRDDRDDR_D19I/O
A10VDDIODDRDDRDDR_D20I/O
D10VDDIODDRDDRDDR_D21I/O
B11VDDIODDRDDRDDR_D22I/O
A11VDDIODDRDDRDDR_D23I/O
J12VDDIODDRDDRDDR_D24I/O
H10VDDIODDRDDRDDR_D25I/O
J11VDDIODDRDDRDDR_D26I/O
K11VDDIODDRDDRDDR_D27I/O
L13VDDIODDRDDRDDR_D28I/O
L11VDDIODDRDDRDDR_D29I/O
L12VDDIODDRDDRDDR_D30I/O
M17VDDIODDRDDRDDR_D31I/O
F12VDDIODDRDDRDDR_A0O
C17VDDIODDRDDRDDR_A1O
B17VDDIODDRDDRDDR_A2O
B16VDDIODDRDDRDDR_A3O
C16VDDIODDRDDRDDR_A4O
G14VDDIODDRDDRDDR_A5O
F14VDDIODDRDDRDDR_A6O
F11VDDIODDRDDRDDR_A7O
C14VDDIODDRDDRDDR_A8O
D13VDDIODDRDDRDDR_A9O
C15VDDIODDRDDRDDR_A10O
A16VDDIODDRDDRDDR_A11O
A17VDDIODDRDDRDDR_A12O
G11VDDIODDRDDRDDR_A13O
E17VDDIODDRDDRDDR_CLKO
D17VDDIODDRDDRDDR_CLKNO
F16VDDIODDRDDRDDR_CKEO
E16VDDIODDRDDRDDR_RESETNO
G13VDDIODDRDDRDDR_CSO
F15VDDIODDRDDRDDR_WEO
F13VDDIODDRDDRDDR_RASO
G12VDDIODDRDDRDDR_CASO
C11VDDIODDRDDRDDR_DQM0O
G15VDDIODDRDDRDDR_DQM1O
C8VDDIODDRDDRDDR_DQM2O
H11VDDIODDRDDRDDR_DQM3O
B13VDDIODDRDDRDDR_DQS0O
J17VDDIODDRDDRDDR_DQS1O
C10VDDIODDRDDRDDR_DQS2O
L17VDDIODDRDDRDDR_DQS3O
B14VDDIODDRDDRDDR_DQSN0O
J16VDDIODDRDDRDDR_DQSN1O
B10VDDIODDRDDRDDR_DQSN2O
L16VDDIODDRDDRDDR_DQSN3O
H12VDDIODDRDDRDDR_BA0O
H13VDDIODDRDDRDDR_BA1O
F17VDDIODDRDDRDDR_BA2O
E13VDDIODDRDDRDDR_CALI
L15, J15, H15, E15, D15, D12, D11VDDIODDRpowerVDDIODDRI
L14, J14, H14, E14, D14, E12, E11GNDIODDRgroundGNDIODDRI
H3, N5, N9, K13, D9, D7VDDCOREpowerVDDCOREI
H4, M5, M9, K12, E9, E7GNDCOREgroundGNDCOREI
E6, F7VDDIOP0powerVDDIOP0I
F6, G7GNDIOP0groundGNDIOP0I
R14, N13VDDIOP1powerVDDIOP1I
M13, P14GNDIOP1groundGNDIOP1I
F10VDDIOP2powerVDDIOP2I
F9GNDIOP2groundGNDIOP2I
P11VDDSDMMCpowerVDDSDMMCI
R11GNDSDMMCgroundGNDSDMMCI
F4VDDISCpowerVDDISCI
G4GNDISCgroundGNDISCI
M12VDDFUSEpowerVDDFUSEI
U4VDDPLLApowerVDDPLLAI
U5GNDPLLAgroundGNDPLLAI
T3VDDAUDIOPLLpowerVDDAUDIOPLLI
T5GNDDPLLgroundGNDDPLLI
T4GNDAUDIOPLLgroundGNDAUDIOPLLI
U3VDDAUDIOPLLCLK_AUDIOO
U7VDDOSCXINI
U6VDDOSCXOUTO
T7VDDOSCpowerVDDOSCI
T6GNDOSCgroundGNDOSCI
P8VDDUTMIIpowerVDDUTMIII
R9VDDHSICpowerVDDHSICI
P9GNDUTMIIgroundGNDUTMIII
T8VDDUTMIIHHSDPAI/O
R8VDDUTMIIHHSDMAI/O
U8VDDUTMIIHHSDPBI/O
U9VDDUTMIIHHSDMBI/O
T9VDDHSICHHSDPDATCI/O
U10VDDHSICHHSDMSTRCI/O
P7VDDUTMICpowerVDDUTMICI
R7GNDUTMICgroundGNDUTMICI
T10VDDSDMMCSDCALI
R6VDDUTMICVBGI
P3VDDBUTSTI
U2VDDBUNRST(3)I
T2VDDBUJTAGSELI
P4VDDBUWKUPI
N4VDDBURXDI
R1VDDBUSHDNO
R3VDDBUPIOBU0I/O
N8VDDBUPIOBU1I/O
R2VDDBUPIOBU2I/O
R5VDDBUPIOBU3I/O
R4VDDBUPIOBU4I/O
P5VDDBUPIOBU5I/O
P6VDDBUPIOBU6I/O
M8VDDBUPIOBU7I/O
N7VDDBUpowerVDDBUI
N6GNDBUgroundGNDBUI
P1VDDBUXIN32I
P2VDDBUXOUT32O
T1VDDBUCOMPPI
U1VDDBUCOMPNI
Note:
  1. Signal = ‘PIO’ if GPIO; Dir = Direction; PU = Pull-up; PD = Pull-down; HiZ = High impedance; ST = Schmitt Trigger
  2. The GPIO reset state is not guaranteed during the power-up phase. During this phase, the GPIOs are in Input Pull-Up mode and they take their reset value only after VDDCORE POR reset has been released. If a GPIO must be at level zero at power-up, it is recommended to connect an external pull-down to ensure this state.
  3. For NRST usage, refer to the section Debug and Test Features.
  4. JTAG boundary scan is available only on JTAG IO Set 1.