36.7.3 MPDDRC Configuration Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	UNAL	DECOD	NDQS	NB	LC_LPDDR1		ENRDM	DQMS
Access	R/W	R/W	R/W	R/W	R/W		R/W	R/W
Reset	0	0	1	0	0		0	0


Bit	15	14	13	12	11	10	9	8
		OCD[2:0]			ZQ[1:0]		DIS_DLL	DIC_DS
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		1	1	1	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DLL	CAS[2:0]			NR[1:0]		NC[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	1	0	0	1	0	0

Bit 23 – UNAL This bit must always be written to 1.

Bit 22 – DECOD Type of Decoding

Value	Name	Description
0	SEQUENTIAL	Method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank.
1	INTERLEAVED	Method for address mapping where banks alternate at each DDR-SDRAM end of page of the current bank.

Bit 21 – NDQS Not DQS.

This bit is found in DDR2-SDRAM devices, in Extended Mode register 1. DQS may be used in Single-ended mode or paired with optional complementary signal NDQS.

To comply with the LPDDR1 standard, DQS must be used in Single-ended mode. NDQS must be disabled.

Value	Name	Description
0	ENABLED	'Not DQS' is enabled.
1	DISABLED	'Not DQS' is disabled.

Bit 20 – NB Number of Banks

If LC_LPDDR1 is set to 1, NB is not relevant.

Value	Name	Description
0	4_BANKS	4-bank memory devices
1	8_BANKS	8 banks. Only possible when using DDR2-SDRAM, low-power DDR2-SDRAM, DDR3-SDRAM, low-power DDR3-SDRAM devices.

Bit 19 – LC_LPDDR1 Low-cost Low-power DDR1

Value	Name	Description
0	NOT_2_BANKS	Any type of memory devices except low-cost, low-density low-power DDR1.
1	2_BANKS_LPDDR1	Low-cost and low-density low-power DDR1. These devices have a density of 32 Mbits and are organized as two internal banks. To use this feature, the user has to define the type of memory and the data bus width (see MPDDRC_MD). The 16-bit memory device is organized as 2 banks, 9 columns and 11 rows. The 32-bit memory device is organized as 2 banks, 8 columns and 11 rows. It is impossible to use two 16-bit memory devices (2 x 32 Mbits) to create one 32-bit memory device (64 Mbits). In this case, it is recommended to use one 32-bit memory device which embeds four internal banks.

Value

Name

Description

0

NOT_2_BANKS

Any type of memory devices except low-cost, low-density low-power DDR1.

1

2_BANKS_LPDDR1

Low-cost and low-density low-power DDR1. These devices have a density of 32 Mbits and are organized as two internal banks. To use this feature, the user has to define the type of memory and the data bus width (see MPDDRC_MD).

The 16-bit memory device is organized as 2 banks, 9 columns and 11 rows.

The 32-bit memory device is organized as 2 banks, 8 columns and 11 rows.

It is impossible to use two 16-bit memory devices (2 x 32 Mbits) to create one 32-bit memory device (64 Mbits). In this case, it is recommended to use one 32-bit memory device which embeds four internal banks.

Bit 17 – ENRDM Enable Read Measure

This feature is not supported during a change frequency. See “CHG_FRQ: Change Clock Frequency During Self-refresh Mode”.

Value	Name	Description
0	OFF	DQS/DDR_DATA phase error correction is disabled
1	ON	DQS/DDR_DATA phase error correction is enabled

Bit 16 – DQMS Mask Data is Shared

Value	Name	Description
0	NOT_SHARED	DQM is not shared with another controller
1	SHARED	DQM is shared with another controller

Bits 14:12 – OCD[2:0] Off-chip Driver

SDRAM Controller supports only two values for OCD (default calibration and exit from calibration). These values MUST always be programmed during the initialization sequence. The default calibration must be programmed first, after which the exit calibration and maintain settings must be programmed.

This field is found only in the DDR2-SDRAM devices.

Value	Name	Description
0	DDR2_EXITCALIB	Exit from OCD Calibration mode and maintain settings
7	DDR2_DEFAULT_CALIB	OCD calibration default

Bits 11:10 – ZQ[1:0] ZQ Calibration

This parameter is used to calibrate DRAM On resistance (Ron) values over PVT.

This field is found only in the low-power DDR2-SDRAM devices and low-power DDR3-SDRAM devices.

Value	Name	Description
0	INIT	Calibration command after initialization
1	LONG	Long calibration
2	SHORT	Short calibration
3	RESET	ZQ Reset

Bit 9 – DIS_DLL Disable DLL

This value is used during the power-up sequence. It is only found in DDR2-SDRAM devices and DDR3-SDRAM devices.

Value	Description
0	Enable DLL.
1	Disable DLL.

Bit 8 – DIC_DS Output Driver Impedance Control (Drive Strength)

This bit name is described as “DS” in some memory data sheets. It defines the output drive strength. This value is used during the power-up sequence.

For DDR3-SDRAM devices, this field is equivalent to ODS, Output Drive Strength.

This bit is found only in DDR2-SDRAM devices and DDR3-SDRAM devices.

Value	Name	Description
0	DDR2_NORMALSTRENGTH_DDR3_RZQ_6	Normal drive strength (DDR2) - RZQ_6 (40 [NOM], DDR3)
1	DDR2_WEAKSTRENGTH_DDR3_RZQ_7	Weak drive strength (DDR2) - RZQ_7 (34 [NOM], DDR3)

Bit 7 – DLL Reset DLL

This bit defines the value of Reset DLL. It is found only in DDR2-SDRAM and DDR3-SDRAM devices.

This value is used during the power-up sequence.

Value	Name	Description
0	RESET_DISABLED	Disable DLL reset
1	RESET_ENABLED	Enable DLL reset

Bits 6:4 – CAS[2:0] CAS Latency

In the case of DDR3-SDRAM devices, the CAS field must be set to 5 and the SHIFT_SAMPLING field must be set to 2. See “SHIFT_SAMPLING: Shift Sampling Point of Data”. This field is not used to set the DDR3-SDRAM. In the case of DDR3-SDRAM devices, the DLL Off mode sets the CAS Read Latency (CRL) and the CAS Write Latency (CWL) to 6. The latency is automatically set by the controller.

Value	Name	Description
2	DDR_CAS2	LPDDR1 CAS Latency 2
3	DDR_CAS3	LPDDR3/DDR2/LPDDR2/LPDDR1 CAS Latency 3
5	DDR_CAS5	DDR3 CAS Latency 5
6	DDR_CAS6	DDR3/LPDDR3 CAS Latency 6

Bits 3:2 – NR[1:0] Number of Row Bits

Value	Name	Description
0	11_ROW_BITS	11 bits to define the row number, up to 2048 rows
1	12_ROW_BITS	12 bits to define the row number, up to 4096 rows
2	13_ROW_BITS	13 bits to define the row number, up to 8192 rows
3	14_ROW_BITS	14 bits to define the row number, up to 16384 rows

Bits 1:0 – NC[1:0] Number of Column Bits

Value	Name	Description
0	DDR9_MDDR8_COL_BITS	9 bits to define the column number, up to 512 columns, for DDR2/DDR3/LPDDR2/LPDDR3-SDRAM  8 bits to define the column number, up to 256 columns, for LPDDR1-SDRAM
1	DDR10_MDDR9_COL_BITS	10 bits to define the column number, up to 1024 columns, for DDR2/DDR3/LPDDR2/LPDDR3-SDRAM 9 bits to define the column number, up to 512 columns, for LPDDR1-SDRAM
2	DDR11_MDDR10_COL_BITS	11 bits to define the column number, up to 2048 columns, for DDR2/DDR3/LPDDR2/LPDDR3-SDRAM SDRAM 10 bits to define the column number, up to 1024 columns, for LPDDR1-SDRAM
3	DDR12_MDDR11_COL_BITS	12 bits to define the column number, up to 4096 columns, for DDR2/DDR3/LPDDR2/LPDDR3-SDRAM 11 bits to define the column number, up to 2048 columns, for LPDDR1-SDRAM

Name:	MPDDRC_CR
Offset:	0x08
Reset:	0x00207024
Property:	Read/Write