46.7.16 TWIHS Receive Holding Register (FIFO Enabled)

If FIFO is enabled (FIFOEN bit in TWIHS_CR), refer to 46.6.6.8 Multiple Data Mode for details.

Name: TWIHS_RHR (FIFO_ENABLED)
Offset: 0x30
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 RXDATA3[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 RXDATA2[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 RXDATA1[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 RXDATA0[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 31:24 – RXDATA3[7:0] Host or Client Receive Holding Data 3

Bits 23:16 – RXDATA2[7:0] Host or Client Receive Holding Data 2

Bits 15:8 – RXDATA1[7:0] Host or Client Receive Holding Data 1

Bits 7:0 – RXDATA0[7:0] Host or Client Receive Holding Data 0