67.23.2 Timing Extraction

Figure 67-39. ISC Timing Diagram

Table 67-96. ISC IOSET1 Timings
Symbol	Power Supply	1.8V		3.3V		Unit
Symbol	Parameter	Min	Max	Min	Max	Unit
ISC₁	DATA setup time before PIXCLK rises	3.9	–	3.6	–	ns
ISC₂	DATA hold time after PIXCLK rises	0.7	–	0.6	–	ns
ISC₃	VSYNC/HSYNC/FIELD setup time before PIXCLK rises	4.4	–	4.2	–	ns
ISC₄	CONTROL VSYNC/HSYNC/FIELD hold time after PIXCLK rises	0.4	–	0.3	–	ns
ISC₅	PIXCLK frequency	–	96	–	96	MHz

Table 67-97. ISC IOSET2 Timings
Symbol	Power Supply	1.8V		3.3V		Unit
Symbol	Parameter	Min	Max	Min	Max	Unit
ISC₁	DATA setup time before PIXCLK rises	4.3	–	4.2	–	ns
ISC₂	DATA hold time after PIXCLK rises	0.5	–	0.3	–	ns
ISC₃	VSYNC/HSYNC/FIELD setup time before PIXCLK rises	4.6	–	4.4	–	ns
ISC₄	CONTROL VSYNC/HSYNC/FIELD hold time after PIXCLK rises	0.2	–	0	–	ns
ISC₅	PIXCLK frequency	–	96	–	96	MHz

Table 67-98. ISC IOSET3 Timings
Symbol	Power Supply	1.8V		3.3V		Unit
Symbol	Parameter	Min	Max	Min	Max	Unit
ISC₁	DATA setup time before PIXCLK rises	4.6	–	4.2	–	ns
ISC₂	DATA hold time after PIXCLK rises	0.5	–	0.4	–	ns
ISC₃	VSYNC/HSYNC/FIELD setup time before PIXCLK rises	4.3	–	4	–	ns
ISC₄	CONTROL VSYNC/HSYNC/FIELD hold time after PIXCLK rises	1.5	–	0.4	–	ns
ISC₅	PIXCLK frequency	–	96	–	96	MHz

Table 67-99. ISC IOSET4 Timings
Symbol	Power Supply	1.8V		3.3V		Unit
Symbol	Parameter	Min	Max	Min	Max	Unit
ISC₁	DATA setup time before PIXCLK rises	4.3	–	4	–	ns
ISC₂	DATA hold time after PIXCLK rises	0.5	–	0.4	–	ns
ISC₃	VSYNC/HSYNC/FIELD setup time before PIXCLK rises	4.2	–	4	–	ns
ISC₄	CONTROL VSYNC/HSYNC/FIELD hold time after PIXCLK rises	0.5	–	0.3	–	ns
ISC₅	PIXCLK frequency	–	96	–	96	MHz

SAMA5D29