51.12.41 SDMMC Preset Value Register
One of the Preset Value registers is effective based on the selected bus speed mode. The table below defines the conditions to select one of the SDMMC_PVRs.
| Selected Bus Speed Mode | VS18EN (SDMMC_HC2R) |
HSEN (SDMMC_HC1R) |
UHSMS (SDMMC_HC2R) |
|---|---|---|---|
| Default Speed | 0 | 0 | don’t care |
| High Speed | 0 | 1 | don’t care |
| SDR12 | 1 | don’t care | 0 |
| SDR25 | 1 | don’t care | 1 |
| SDR50 | 1 | don’t care | 2 |
| SDR104/HS200 | 1 | don’t care | 3 |
| DDR50 | 1 | don’t care | 4 |
| Reserved | 1 | don’t care | Other values |
The table below shows the effective Preset Value Register according to the Selected Bus Speed mode.
| SDMMC_PVRx | Selected Bus Speed Mode | Signal Voltage |
|---|---|---|
| SDMMC_PVR0 | Initialization | 3.3V or 1.8V |
| SDMMC_PVR1 | Default Speed | 3.3V |
| SDMMC_PVR2 | High Speed | 3.3V |
| SDMMC_PVR3 | SDR12 | 1.8V |
| SDMMC_PVR4 | SDR25 | 1.8V |
| SDMMC_PVR5 | SDR50 | 1.8V |
| SDMMC_PVR6 | SDR104/HS200 | 1.8V |
| SDMMC_PVR7 | DDR50 | 1.8V |
When Preset Value Enable (PVALEN) in SDMMC_HC2R is set to 1, Driver Strength Select (DRVSEL) in SDMMC_HC2R and SDCLK Frequency Select (SDLCKFSEL) and Clock Generator Select (CLKGSEL) in SDMMC_CCR are automatically set based on the Selected Bus Speed mode. This means that the user does not need to set these fields when preset is enabled. A Preset Value Register for Initialization (SDMMC_PVR0) is not selected by Bus Speed mode. Before starting the initialization sequence, the user needs to set a clock preset value to SDCLKFSEL in SDMMC_CCR.PVALEN can be set to 1 after the initialization is completed.
| Name: | SDMMC_PVRx |
| Offset: | 0x60 + x*0x02 [x=0..7] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DRVSEL[1:0] | CLKGSEL | SDCLKFSEL[9:8] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SDCLKFSEL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:14 – DRVSEL[1:0] Driver Strength Select
See DRVSEL in SDMMC_HC2R (SD_SDIO) / SDMMC_HC2R (e.MMC).
Bit 10 – CLKGSEL Clock Generator Select
See CLKGSEL in SDMMC_CCR.
Bits 9:0 – SDCLKFSEL[9:0] SDCLK Frequency Select
See SDCLKFSEL in SDMMC_CCR.