47.10.72 TWI Receive Holding Register (FIFO Enabled)
To read multi-data, the FIFO must be enabled (FLEX_TWI_CR.FIFOEN=1) and
Sniffer mode disabled (FLEX_TWI_SMR.SNIFF=0). The access type (byte, halfword or word)
determines the number of data written in a single access (1, 2 or 4), see TWI Multiple Data Access for details.
Name: | FLEX_TWI_RHR (FIFO_ENABLED) |
Offset: | 0x630 |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RXDATA3[7:0] | |
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RXDATA2[7:0] | |
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RXDATA1[7:0] | |
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXDATA0[7:0] | |
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:24 – RXDATA3[7:0] Host or Client Receive Holding Data
3
Bits 23:16 – RXDATA2[7:0] Host or Client Receive Holding Data
2
Bits 15:8 – RXDATA1[7:0] Host or Client Receive Holding Data
1
Bits 7:0 – RXDATA0[7:0] Host or Client Receive Holding Data
0