47.8.3.2 Host Mode Flowchart
![](GUID-0365CAFA-672B-492B-B560-B51D5B4858D2-low.png)
The following figure shows the behavior of Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags within FLEX_SPI_SR during an 8-bit data transfer in Fixed mode without the DMAC involved.
![](GUID-4B34AF3E-DB08-4E5A-964F-597AA04CD916-low.png)