47.10.57 SPI Comparison Register

This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register.

Name: FLEX_SPI_CMPR
Offset: 0x448
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 VAL2[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 VAL2[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 VAL1[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 VAL1[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:16 – VAL2[15:0] Second Comparison Value for Received Character

ValueDescription
0–65535

The received character must be lower than or equal to the value of VAL2 and higher than or equal to VAL1 to set the FLEX_SPI_CSR.CMP flag. If asynchronous partial wakeup is enabled in PMC_SLPWK_ER, the SPI requests a system wakeup if condition is met.

Bits 15:0 – VAL1[15:0] First Comparison Value for Received Character

ValueDescription
0–65535

The received character must be higher than or equal to the value of VAL1 and lower than or equal to VAL2 to set the FLEX_SPI_SR.CMP flag. If asynchronous partial wakeup is enabled in PMC_SLPWK_ER, the SPI requests a system wakeup if the condition is met.