15.5.13 L2CC Masked Interrupt Status Register
The following configuration values are valid for all listed bit names of this register:
0: No interrupt has been generated or the interrupt is masked.
1: The input lines have triggered an interrupt.
Name: | L2CC_MISR |
Offset: | 0x218 |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | DECERR | |
Access | | | | | | | | R | |
Reset | | | | | | | | 0 | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SLVERR | ERRRD | ERRRT | ERRWD | ERRWT | PARRD | PARRT | ECNTR | |
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 8 – DECERR DECERR from L3 memory
Bit 7 – SLVERR SLVERR from L3 memory
Bit 6 – ERRRD Error on L2 Data RAM, Read
Bit 5 – ERRRT Error on L2 Tag RAM, Read
Bit 4 – ERRWD Error on L2 Data RAM, Write
Bit 3 – ERRWT Error on L2 Tag RAM, Write
Bit 2 – PARRD Parity Error on L2 Data RAM, Read
Bit 1 – PARRT Parity Error on L2 Tag RAM, Read
Bit 0 – ECNTR Event Counter 1/0 Overflow Increment