67.17 TWI Timings

Figure 67-25. Two-wire Serial Bus Timing

The table below describes the requirements for devices connected to the Two-wire Serial Bus.

Table 67-70. Two-wire Serial Bus Requirements
Symbol Parameter Conditions Min Max Unit
VIL Input Low-voltage – -0.3 0.3 × VDDIO V
VIH Input High-voltage – 0.7 × VDDIO VCC + 0.3 V
Vhys Hysteresis of Schmitt Trigger Inputs – 0.150 – V
VOL Output Low-voltage 3 mA sink current – 0.4 V
tr Rise Time for both TWD and TWCK – 20 + 0.1Cb(2) 300 ns
tfo Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF


(see the figure above)

 20 + 0.1Cb(2) 250 ns
Ci(1) Capacitance for each I/O Pin – – 10 pF
fTWCK TWCK Clock Frequency – 0 400 kHz
Rp Value of Pull-up Resistor fTWCK≤ 100 kHz (VDDIO - 0.4V) ÷ 3mA 1000ns ÷ Cb Ω
fTWCK > 100 kHz (VDDIO - 0.4V) ÷ 3mA 300ns ÷ Cb Ω
tLOW Low Period of the TWCK Clock fTWCK≤ 100 kHz (3) – μs
fTWCK > 100 kHz (3) – μs
tHIGH High Period of the TWCK Clock fTWCK≤ 100 kHz (4) – μs
fTWCK > 100 kHz (4) – μs
th(start) Hold Time (repeated) START condition fTWCK≤ 100 kHz tHIGH – μs
fTWCK > 100 kHz tHIGH – μs
tsu(start) Setup Time for a Repeated START condition fTWCK≤ 100 kHz tHIGH – μs
fTWCK > 100 kHz tHIGH – μs
th(data) Data Hold Time fTWCK≤ 100 kHz 0 (HOLD + 3) × tperipheral clock μs
fTWCK > 100 kHz 0 (HOLD + 3) × tperipheral clock μs
tsu(data) Data Setup Time fTWCK≤ 100 kHz tLOW - (HOLD + 3) × tperipheral clock – ns
fTWCK > 100 kHz tLOW - (HOLD + 3) × tperipheral clock – ns
tsu(stop) Setup time for STOP condition fTWCK≤ 100 kHz tHIGH – μs
fTWCK > 100 kHz tHIGH – μs
tBUF Bus free time between a STOP and START condition fTWCK≤ 100 kHz tLOW – μs
fTWCK > 100 kHz tLOW – μs

Note:
  1. Required only for fTWCK > 100 kHz.
  2. CB = capacitance of one bus line in pF. Per I2C Standard, Cb Max = 400 pF
  3. The TWCK low period is defined as follows: tLOW = ((CLDIV × 2CKDIV) + 3) × tMCK
  4. The TWCK high period is defined as follows: tHIGH = ((CHDIV × 2CKDIV) + 3) × tMCK