67.17 TWI Timings

Figure 67-25. Two-wire Serial Bus Timing

The table below describes the requirements for devices connected to the Two-wire Serial Bus.

Table 67-70. Two-wire Serial Bus Requirements
SymbolParameterConditionsMinMaxUnit
VILInput Low-voltage–-0.30.3 × VDDIOV
VIHInput High-voltage–0.7 × VDDIOVCC + 0.3V
VhysHysteresis of Schmitt Trigger Inputs–0.150–V
VOLOutput Low-voltage3 mA sink current–0.4V
trRise Time for both TWD and TWCK–20 + 0.1Cb(2)300ns
tfoOutput Fall Time from VIHmin to VILmax10 pF < Cb < 400 pF


(see the figure above)

20 + 0.1Cb(2)250ns
Ci(1)Capacitance for each I/O Pin––10pF
fTWCKTWCK Clock Frequency–0400kHz
RpValue of Pull-up ResistorfTWCK≤ 100 kHz(VDDIO - 0.4V) ÷ 3mA1000ns ÷ CbΩ
fTWCK > 100 kHz(VDDIO - 0.4V) ÷ 3mA300ns ÷ CbΩ
tLOWLow Period of the TWCK ClockfTWCK≤ 100 kHz(3)–μs
fTWCK > 100 kHz(3)–μs
tHIGHHigh Period of the TWCK ClockfTWCK≤ 100 kHz(4)–μs
fTWCK > 100 kHz(4)–μs
th(start)Hold Time (repeated) START conditionfTWCK≤ 100 kHztHIGH–μs
fTWCK > 100 kHztHIGH–μs
tsu(start)Setup Time for a Repeated START conditionfTWCK≤ 100 kHztHIGH–μs
fTWCK > 100 kHztHIGH–μs
th(data)Data Hold TimefTWCK≤ 100 kHz0(HOLD + 3) × tperipheral clockμs
fTWCK > 100 kHz0(HOLD + 3) × tperipheral clockμs
tsu(data)Data Setup TimefTWCK≤ 100 kHztLOW - (HOLD + 3) × tperipheral clock–ns
fTWCK > 100 kHztLOW - (HOLD + 3) × tperipheral clock–ns
tsu(stop)Setup time for STOP conditionfTWCK≤ 100 kHztHIGH–μs
fTWCK > 100 kHztHIGH–μs
tBUFBus free time between a STOP and START conditionfTWCK≤ 100 kHztLOW–μs
fTWCK > 100 kHztLOW–μs

Note:
  1. Required only for fTWCK > 100 kHz.
  2. CB = capacitance of one bus line in pF. Per I2C Standard, Cb Max = 400 pF
  3. The TWCK low period is defined as follows: tLOW = ((CLDIV × 2CKDIV) + 3) × tMCK
  4. The TWCK high period is defined as follows: tHIGH = ((CHDIV × 2CKDIV) + 3) × tMCK