54.6.3 Clock Selection

Input clock signals of each channel can be connected either to the external inputs TCLKx, or to the internal I/O signals TIOAx for chaining⁽¹⁾ by programming the Block Mode register (TC_BMR). See the figure Clock Chaining Selection.

Each channel can independently select a source for its counter⁽²⁾:

Signals from other channels: XC0, XC1 or XC2
Signals from the system: GCLK [35], GCLK [36], System bus clock divided by 8, System bus clock divided by 32, System bus clock divided by 128, TD_SLCK

This selection is made by the TCCLKS bits in the Channel Mode register (TC_CMRx).

The selected clock can be inverted with TC_CMRx.CLKI. This allows counting on the opposite edges of the clock.

The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the TC_CMRx defines this signal (none, XC0, XC1, XC2). See the figure Clock Selection.

Note:

In Waveform mode, to chain two timers, it is mandatory to initialize some parameters: 
- Configure TIOx outputs to 1 or 0 by writing the required value to TC_CMRx.ASWTRG.
- Bit TC_BCR.SYNC must be written to 1 to start the channels at the same time.
In all cases, if an external clock or asynchronous internal clock GCLK is used, the duration of each of its levels must be longer than the peripheral clock period, so the clock frequency will be at least 2.5 times lower than the peripheral clock.

Note: This figure provides pin names of a first instance of a Timer Counter block (i.e., instance TC0). For any subsequent instances, the signal numbering increments. For example, “TCLK3-TCLK5”, "TIOA3-TIOA5” and "TIOB3-TIOB5” are the external clock input pins of a second Timer Counter block (i.e., instance TC1).