67.19.4 LPDDR2/LPDDR3-SDRAM

Note: For LPDDR2/LPDDR3 memory, the SHIFT_SAMPLING field value in the MPRDDRC_RD_DATA_PATH register must be configured as follows:

SHIFT_SAMPLING = 0 for 0 < DDR_CLK < 80 MHz

SHIFT_SAMPLING = 1 for 80 MHz < DDR_CLK < 166 MHz

Table 67-80. System Clock Waveform Parameters
SymbolParameterConditionsMinMaxUnit
tDDRCKDDRCK Cycle TimeVDDCORE[1.1V, 1.32V]7.5–ns
tDDRCKDDRCK Cycle TimeVDDCORE[1.1V, 1.32V],
VDDIODDR[1.18V, 1.3V]6–ns