15.5.15 L2CC Interrupt Clear Register

The following configuration values are valid for all listed bit names of this register:

0: No effect. Read returns zero.

1: Clears the corresponding bit in the Raw Interrupt Status Register.

Name: L2CC_ICR
Offset: 0x220
Reset: 0x00000000
Property: Programmable in Auxiliary Control register.

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
        DECERR 
Access  
Reset 0 
Bit 76543210 
 SLVERRERRRDERRRTERRWDERRWTPARRDPARRTECNTR 
Access  
Reset 00000000 

Bit 8 – DECERR DECERR from L3 memory

Bit 7 – SLVERR SLVERR from L3 memory

Bit 6 – ERRRD Error on L2 Data RAM, Read

Bit 5 – ERRRT Error on L2 Tag RAM, Read

Bit 4 – ERRWD Error on L2 Data RAM, Write

Bit 3 – ERRWT Error on L2 Tag RAM, Write

Bit 2 – PARRD Parity Error on L2 Data RAM, Read

Bit 1 – PARRT Parity Error on L2 Tag RAM, Read

Bit 0 – ECNTR Event Counter 1/0 Overflow Increment